• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.784-786
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• 2000

This paper implements and analyzes logically the Borrow Look-ahead Subtracter using Borrow Generator and Borrow Propagator. In subtracting calculation, we improve the calculating efficiency with using 4-bit subtracter which has Borrow Look-ahead Subtracters connection, and show that this is compatible with adder using the concept of Carry Generator and Carry Propagator. This subtracter may be useful in frequent subtracting calculation. We think this approach makes it possible to implement simple ALU(Arithmetic Logic Unit) with combining the concept of Borrow Look-ahead Subtracter and Carry Look-ahead Adder.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• 한국초전도ㆍ저온공학회논문지
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• 제4권1호
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• pp.35-39
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• 2002

We have simulated and laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. SFQ AND gate circuit is a combination of two D Flip-Flop. D Flip-Flop and dc SQUID are the similar shape form the fact that it has the loop inductor and two Josephson junction We obtained perating margins and accomplished layout of the AND gate. We got the margin of $\pm$38%. over. After layout, we drew mask for fabrication of SFQ AND sate. This mask was included AND gate, dcsfq, sfqdc, rs flip-flop and jtl.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 하계학술대회 논문집
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• pp.471-474
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• 1990

In this paper, a vision-based inspection algorithm for checking mark quality on an integrated chip(IC) is proposed. In order to reduce the processing time for inspection, we are implemented image arithmetic unit and binary image projection processor in hardware. By adopting the hardwares, the processing time becomes less one sixth of that in case of using software only.

• 한국통신학회논문지
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• 제25권5A호
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• pp.702-708
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• 2000

본 논문에서는 프랙탈 영상압축의 고속수행을 위한 최적의 파이프라인 주기를 갖는 일차원 VLSI 어레이를 설계했다. 고정분할 알고리즘을 변형하여 VLSI 어레이 설계에 적합하며 화질의 손상을 최소화하면서 압축율이 높은 알고리즘을 유도했다. 파이프라인의 각 세그먼트를 구성하는 PE의 연산시간을 가능한 균등하게 분포시켜 최적의 파이프라인의 주기를 얻었다. 이러한 결과로써 약 4배의 속도 향상을 얻을 수 있다. 정의역과 치역블럭의 입출력과 연산장치를 공유하여 입출력 핀의 수를 줄였다.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 학술대회 논문집
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• pp.92-94
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• 2003

In superconductive digital logic circuits, D2 cells can be used to compose a decoder an important component of an Arithmetic Logic Unit (ALU). In this wor, we simulated D2 cell by using WRspice. D2 cell has one input, one switch input, and two outputs (output1 and output2). D2 cell functions in such way that output1 follows the input and output2 is the complement of the input data, when the switch input is "0, ". However, when there is a switch input "1, " the opposite output signals are generated. In this paper, we optimized a D2 cell by using WRspice, and obtained the minimum margin of 26%. Our optimized D2 cell will play a key role in the ALU fabrication.the ALU fabrication.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• 정보학연구
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• 제5권4호
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• pp.145-154
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• 2002

기수확장(Extension of Base)은 잉여수계(RNS:Residue Number System)에서 모듈리를 확장하기 위한 기본적인 방법이다. 잉여수계는 병렬성과 모듈간의 자리올림 수의 전달이 없는 장점을 갖지만, 기수확장 등에 의해 전체적인 시스템의 성능이 저항되며, 혼합기수 변환을 적용한 기존의 방법에서는 연산기의 크기는 감소하지만 연산속도가 저하되는 문제점을 갖는다. 그러므로, 본 논문에서는 CRT를 사용한 개선된 기수확장을 수행하여, 비교적 적은 크기이며, 속도가 향상된 기수 확장기를 설계할 수 있었다.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.117-119
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• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.76-78
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• 2003

We have designed and tested an RSFQ (Rapid Single Flux Quantum) NDRO (Non Destructive Read Out) circuit for the development of a high speed superconducting ALU (Arithmetic Logic Unit). When designing the NDRO circuit, we used Julia, XIC and Lmeter for the circuit simulations and layouts. We obtained the simulation margins of larger than $\pm$25％. For the tests of NDRO operations, we attached the three DC/SFQ circuits and two SFQ/DC circuits to the NDRO circuit. In tests, we used an input frequency of 1 KHz to generate SFQ Pulses from DC/SFQ circuit. We measured the operation bias margin of NDRO to be $\pm$15％. The circuit was measured at the liquid helium temperature.