• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• Education of Primary School Mathematics
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• v.16 no.3
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• pp.251-266
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• 2013

With elementary school students who have learned the primary concepts of the four arithmetic operations as its subjects, this study has investigated in depth how schema and transformed schema are composed by recognition of the correct concepts and connection of concepts, that is to say, what schema learners form along with transformed schema with the primary concepts of the four arithmetic operations to understand the secondary concepts when power and mixed calculations are taken into contents. It has also investigated how the subjects use the schema they have formed for themselves and the transformed schema to approach problem solving, and how their composition of concepts and schema in problem solving ability achieve transformations. As a result, we can tell that the recognition of precise primary concepts and transformed schema work as important factors in the development from the primary to the secondary concepts. Here, we can also see learn that the formation of the schema created due to the connection among the primary concepts and the recognition of them and of the transformed schema play more important roles in the development toward the secondary concepts and the solution of arithmetic problems than any other factors.

• The KIPS Transactions:PartC
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• v.17C no.3
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• pp.233-242
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• 2010

In the recent years, power attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate results in the algorithm computations(encryption, decryption) are well-known. In case of SEED block cipher, it uses 32 bit arithmetic addition and S-box operations as non-linear operations. Therefore the masking type conversion operations, which require some operating time and memory, are required to satisfy the masking method of all non-linear operations. In this paper, we propose a new masked S-boxes that can minimize the number of the masking type conversion operation. Moreover we construct just one masked S-box table and propose a new formula that can compute the other masked S-box's output by using this S-box table. Therefore the memory requirements for masked S-boxes are reduced to half of the existing masking method's one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.140-142
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• 2011

In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

• Journal of Educational Research in Mathematics
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• v.21 no.3
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• pp.239-259
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• 2011

This study investigated the elementary school students' ability on the algebraic reasoning as generalized arithmetic. It analyzed the written responses from 648 second graders, 688 fourth graders, and 751 sixth graders using tests probing their understanding of the properties of whole number operations. The result of this study showed that many students did not recognize the properties of operations in the problem situations, and had difficulties in applying such properties to solve the problems. Even lower graders were quite successful in using the commutative law both in addition and subtraction. However they had difficulties in using the associative and the distributive law. These difficulties remained even for upper graders. As for the associative and the distributive law, students had more difficulties in solving the problems dealing with specific numbers than those of arbitrary numbers. Given these results, this paper includes issues and implications on how to foster early algebraic reasoning ability in the elementary school.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.7 no.1
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• pp.85-89
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• 2007

Many authors considered the computational aspect of sup-min convolution when applied to weighted average operations. They used a computational algorithm based on a-cut representation of fuzzy sets, nonlinear programming implementation of the extension principle, and interval analysis. It is well known that $T_W$(the weakest t-norm)-based addition and multiplication preserve the shape of L-R type fuzzy numbers. In this paper, we consider the computational aspect of the extension principle by the use of $T_W$ when the principle is applied to fuzzy weighted average operations. We give the exact solution for the case where variables and coefficients are L-L fuzzy numbers without programming or the aid of computer resources.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.187-193
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• 2020

Floating point arithmetic in microprocessor is the computation of addition, subtraction, multiplication, and division of floating point data to improve accuracy. In general, when designing a processor, floating point instructions are often excluded because of its complexity and only integer instructions are provided. However, in order to carry out the computations for not only engineering and technical operations but also artificial intelligence and neural networks that are in the spotlight today, floating point operations must be included. In this paper, we design a 32-bit ARMv4 family of processors with floating-point arithmetic instructions using VHDL and verify with ModelSim. As a result, ARM's floating point instructions are successfully executed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1098-1103
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• 2005

The edge and contour information are very much appreciated by the human visual systems and are responsible for our perceptions and recognitions. Therefore, if edge information is integrated during extracting video objects, we can generate boundaries of oects closer to human visual systems for multimedia applications such as interaction between video objects, object-based coding, and representation. Most of object extraction methods are difficult to implement real-time systems due to their iterative and complex arithmetic operations. In this paper, we propose a VLSI architecture integrating edge information to extract video objects for precisely located object boundaries. The proposed architecture can be easily implemented into hardware due to simple arithmetic operations. Also, it can be applied to real-time object extraction for object-oriented multimedia applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.540-543
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• 2013

This paper describes an implementation of a unified ALU on multi-core GPGPU based on SIMT architecture. Our unified ALU can operate conditional branch instructions, data movement instructions, integer arithmetic instructions and floating-point arithmetic instructions. Since multi-core GPGPU contains a lot of ALU for parallel processing of various types, the main point of this paper is to design the minimum size ALU by unifying similar processing of each operations on circit level. All instrunctions were tested by making a test program. And we compare this results with results of CPU operations to verify our ALU. Our unified ALU's gate size is approximately 20,000 and the maximum operation frequency is 430MHz.