• 전자공학회논문지B
• /
• 제30B권5호
• /
• pp.27-33
• /
• 1993

This paper describes the hardware implementation of 2-D FIR digital filter for a real-time image processing. Generally, the most time-consuming operation in signal processing is the multiplication operation. To avoid it in digital filter. Pelid and Liu proposed the distributed arithmetic method for the one-dimensional case. The implementation method proposed in this paper is to extend Pelid's method to two-dimensional FIR filter using simple ROM lookup table and to use the technique of pipe lining two main operations of memory access and arithmetic. As a result, the speed of our proposed hardware implementation is two times faster than that of conventional methods and can be close to the real time speed.

• 산업경영시스템학회지
• /
• 제8권12호
• /
• pp.127-138
• /
• 1985

There are several methods which have been presented up to now in solving the simultaneous linear equations by computer. They are Gaussian Elimination Method, Gauss-Jordan Method, Inverse matrix Method and Gauss-Seidel iterative Method. This paper is not only discussed in their mechanisms compared with their algorithms, depicted flow charts, but also calculated the numbers of arithmetic operations and comparisons in order to criticize their availability. Inverse Matrix Method among em is founded out the smallest in the number of arithmetic operation, but is not the shortest operation time. This paper also indicates the many problems in using these methods and propose the new method which is able to applicate to even small or middle size computers.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.1125-1128
• /
• 1998

A new architecture for high-speed implementation of adaptive decision-feedback equalizer (ADFE) applicable to wide-band digital wireless modems is described. Rather than using conventional two's complement arithmetic, a novel complex-valued filter structure is devised, which is based on redundant binary (RB) arithmetic. The proposed RB complex-valued filter reduces the critical path delay of ADFE, as well as leads to a more compact implementation than conventional methods. Also, the carry-propagation free (CPF) operation of the RB arithmetic enhances its speed. To demonstrate the proposed method, a prototype chip set is designed. They are designed to contain two complexvalued filter taps along with their coefficient updating circuits, and can be cascaded to implement loger filter taps for high bit-rate applications.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
• /
• pp.778-780
• /
• 1999

Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

• 전자공학회논문지A
• /
• 제31A권6호
• /
• pp.188-198
• /
• 1994

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

• 한국수학교육학회지시리즈A:수학교육
• /
• 제51권4호
• /
• pp.429-453
• /
• 2012

The purpose of the study were to analyze teaching models of arithmetic operations of integers in Korean middle school mathematics textbooks of the first grade and Americans', from which we compare and analyze standards for choice of models of middle school teachers and preservice mathematics teachers. We also analyze the effect of the choice of teaching models for students to understand and appreciate number systems as a coherent body of knowledge. On the basis of that, we would like to find the best model to help students understand and reason the process of formulate the arithmetic operations of natural numbers and integers into the operation of the real number system. Furthermore, we help these series of the study to be applied effectively in the middle school mathematics class in Korea.

• 정보과학회지
• /
• 제3권1호
• /
• pp.18-30
• /
• 1985

三値논리는 同一의 情報量을 表現하는데 二値에 비하여 적은수의 記號로 써 達成할 수 있고 演算速度가 빠르다는 특징을 갖고 있다. 그러나 현재로서는 回路素子가 三値論理에 適合한 것이 나와 있지 않고 二値論理만큼 工學的인 接近 이 이루어져 있지 않은 상태이지만 보다 고 속의 情報處理裝置를 構成하기 위해 서 이 分野의 硏究는 價値있는 일이라 하겠다. 三値論理에 對해서는 Post(1),, M hldorf(2) 이래 많은 硏究가 있었다.

• 디지털산업정보학회논문지
• /
• 제18권1호
• /
• pp.1-9
• /
• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 학술대회지
• /
• pp.636-639
• /
• 2004

In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

• 한국통신학회논문지
• /
• 제29권1C호
• /
• pp.35-44
• /
• 2004

본 논문은 차세대 정지영상 압축방식인 JPEG2000 코덱의 엔트로피 코딩 알고리즘의 하드웨어적 구조를 제안하고, 설계하였다. 구현된 엔트로피 코더는 컨텍스트 기반의 산술부호화기로서 컨텍스트 추출부(CE)와 산술부호화기(AC)로 구성된다. CE는 각 코팅패스에서 코딩에 참여하지 않는 샘플은 skipping 함으로써 동작속도를 향상시켰으며, AC는 MQ coder에 기반을 둔 산술부호화기로서, 곱셈과 나눗셈 연산대신 단순 가감산과 shift 연산망을 이용하여 구조를 단순화하고 연산량을 줄임으로써 동작속도를 향상시켰다. 설계된 엔트로피 코더는 VHDL 모델링후 Xilinx FPGA technology를 이용하여 합성한 후 동작을 검증하였으며, 30MHz의 동작속도를 보인다.