• Journal of Communications and Networks
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• v.17 no.2
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• pp.133-144
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• 2015

In this paper, we introduce a system and a set of algorithms for disseminating popular content to a large group of wireless clients spread over a wide area. This area is partitioned into multiple cells and there is a base station in each cell which is able to broadcast to the clients within its radio coverage. Dissemination of information in the proposed system is hybrid in nature: Each base station broadcasts a fraction of information in the form of random linear combinations of data blocks. Then the clients cooperate by exchanging packets to obtain their desired messages while they are moving arbitrarily over the area. In this paper, fundamental trade-offs between the average information delivery completion time at the clients and different parameters of the system such as bandwidth usage by the base stations, average energy consumption by the clients and the popularity of the spread information are studied. Moreover different heuristic algorithms are proposed to control and maintain a balance over these trade-offs. Also, the more complicated case of multiple sessions where each client is interested in an arbitrary subset of sessions is considered and two variants of the basic dissemination algorithm are proposed. The performance of all the proposed algorithms is evaluated via extensive numerical experiments.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.231-239
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• 2007

This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.9-18
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• 2010

High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.1-7
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• 1999

In this research, transformation-based optimization techniques for pipelined designs have been developed. The transformation-based optimization techniques include pipelined architecture transformations and retiming transformations. The new transformation method has the following three features. First, the overall performance of a pipelined system is optimized owing to various transformations including retiming of multiple pipelined blocks. Second, these techniques can be used to search a large solution space by allowing efficient exploration of trade-offs between area and performance. Third, these techniques can be easily extended to a new transformation or algorithm and can be used to optimize memory or bus architectures. Experimental results illustrate that these transformation-based optimization techniques improve area by 21% and performance by 17% on the average for a set of pipelined designs. Especially, the techniques are useful to efficiently explore a large design space.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.866-869
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• 2015

With the advance in semiconductor technology, the number of elements that can be integrated in system-on-chip(SoC) increases exponentially, and thus voltage scaling is indispensable to enhance energy efficiency. Near-threshold voltage computing(NTC) improves the energy efficiency by an order of degree, hence it is able to overcome the limitation of conventional super-threshold voltage computing(STC). Although NTC-based low performance manycore system can be used to maximize energy efficiency, it demands more number of cores to sustain the performance, which results in considerable increase of area. In this paper, we analyze NTC manycore architecture considering the trade-offs between performance, power, and area. Therefore, we propose an algorithmic methodology that can optimize power consumption and area while satisfying the required performance by determining the constrained number of cores and size of caches and clusters in NTC environment. Experimental results show that proposed NTC architecture can reduce power consumption by approximately 16.5 % while maintaining the performance of STC core under area constraint.

• Proceedings of the SAREK Conference
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• 2006.06a
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• pp.639-644
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• 2006

The outlet temperature of gas cooler has a great effect on the efficiency of carbon dioxide heat pump system. In order to obtain a small approach temperature difference at gas cooler, near-counter flow type heat exchanger has been proposed, and larger heat transfer area is demanded. The optimum design of gas cooler involving the analysis of trade-offs between heat transfer performance and cost is desirable. In this study, the effects of geometric parameters, such as the circuit arrangement, tube diameter, transverse tube spacing, longitudinal tube spacing and the number of tube rows and fin spacing on the performance of heat transfer were investigated using the developed model. This study suggested various simulation results for optimum designs of gas cooler.

• Advances in Computational Design
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• v.3 no.4
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• pp.385-404
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• 2018

The study investigated an area of sustainable structural design that is often overlooked in practical engineering applications. Specifically, a novel method to simultaneously optimise the cost and embodied carbon performance of steel building structures was explored in this paper. To achieve this, a parametric design model was developed to analyse code compliant structural configurations based on project specific constraints and rigorous testing of various steel beam sections, floor construction typologies (precast or composite) and column layouts that could not be performed manually by engineering practitioners. Detailed objective functions were embedded in the model to compute the cost and life cycle carbon emissions of the different material types used in the structure. Results from a comparative numerical analysis of a real case study illustrated that the proposed optimisation approach could guide structural engineers towards areas of the solution space with realistic design configurations, enabling them to effectively evaluate trade-offs between cost and carbon performance. This significant contribution implied that the optimisation model could reduce the time required for the design and analysis of multiple structural configurations especially during the early stages of a project. Overall, the paper suggested that the deployment of automated design procedures can enhance the quality as well as the efficiency of the optimisation analysis.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.821-829
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• 1991

In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.171-176
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• 2006

In this paper, we develop energy efficient designs for the Fast Fourier Transform (FFT) on FPGAs. Architectures for FFT on FPGAs are designed by investigating and applying techniques for minimizing the energy dissipation. Architectural parmeters such as degrees of vertical and horizontal parallelism are identified and a design choices. We determine design trade-offs using high-level performance estimation to obtain energy-efficient designs. We implemented a set storage types as parameters, on Xilinx Vertex-II FPGA to verify the estimates. Our designs dissipate 57% to 78% less energy than the optimized designs from the Xilinx library. In terms of a comprehensive metric such as EAT (Energy-Area-Time), out designs offer performance improvements of 3-13x over the Xilinx designs.