• Architectural research
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• v.18 no.2
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• pp.59-64
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• 2016

Since the massive power outages that hit across the nation in September 2011, a growing imbalance between energy supply and demand has led to a severe backup power shortage. To overcome the energy crisis which is annually repeated, a policy change for deriving energy supply from renewable energy sources and a demand reduction strategy has become essential. Buildings account for 18% of total energy consumption and have great potential for energy efficiency improvements; it is an area considered to be a highly effective target for reducing energy demand by improving buildings' energy efficiency. In this regard, retrofitting buildings to promoting environmental conservation and energy reduction through the reuse of existing buildings can be very effective and essential for reducing maintenance costs and increasing economic output through energy savings. In this study, we compared the energy reduction efficiency of national power energy consumption by unit production volume based on thermal power generation, renewable energy power generation, and initial and operating costs for a building retrofit. The unit production was found to be 13,181GWh/trillion won for bituminous coal-fired power generation, and 5,395GWh/trillion won for LNG power generation, implying that LNG power generation seemed to be disadvantageous in terms of unit production compared to bituminous coal-fired power generation, which was attributable to a difference in unit production price. The unit production from green retrofitting increased to 38,121GWh/trillion won due to the reduced energy consumption and benefits of greenhouse gas reduction costs. Renewable energy producing no greenhouse gas emissions during power generation and showed the highest unit production of 75,638GWh/trillion won, about 5.74 times more effective than bituminous coal-fired power generation.

• Journal of Korean Society on Water Environment
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• v.25 no.6
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• pp.886-895
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• 2009

The guideline of selection of Integrated Management Practices (IMPs), such as wood, green roof, lawn, and porous pavement, for Low Impact Development (LID) design was proposed by ranking the reduction rate of surface runoff using LIDMOD1.0. Based on the guideline, LID was designed with several scenarios at two apartment complexes located at Songpa-gu, Seoul, Korea, and the effect of LID on surface runoff was evaluated during last 10 years. The effect of runoff reduction of IMP by land use change was highly dependent on the kind of hydrologic soil group. The wood planting is the best IMPs for reduction of surfac runoff for all hydrologic soil groups. Lawn planting is an excellent IMP for hydrologic soil group A, but reduction rate is low where soil doesn't effectively drains precipitation. The green roof shows constant reduction rate of surface runoff because it is not influenced by hydrologic soil group. Compared to the rate of other IMPs, the green roof is less effect the surface runoff reduction for hydrologic soil group A and is more effect for hydrologic soil group C and D followed to planing wood. The porous pavement for the impervious area is IMPs which is last selected for LID design because of the lowest reduction rate for all hydrologic soil group. As a result of LID application at study areas, we could conclude that the first step of the strategy of LID design at apartment complex is precuring pervious land as many area as possible, second step is selecting the kind of plant as more interception and evapotranspiration as possible, last step is replacing impervious land with porous pavement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.879-885
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• 2002

The performance of communication systems should be tested against a set of requirements. To this end, noise generation systems are used to generate noise signals with specified characteristics. In this paper, we propose the area & power-efficient noise generation system based on DCT method. It is shown that the proposed structure results in area reduction of non-DCT block by 44∼47%. Moreover, since the proposed structure does not use high-speed internal clock, it achieves power reduction by 74∼77%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.270-276
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• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.58-64
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• 2003

Noise generation systems are used to generate noise signals with specified characteristics. In recent study, DCT-based noise generation system outperforms the conventional noise generation system when a noise model requires complicated PSD(Power Spectral Density) specifications. In this paper, we propose the area-efficient noise generation system based on DCT method. It is shown that the proposed system results in area reduction by 61~64% except DCT block. Furthermore, it achieves power reduction by 41~56%.

• Proceedings of the Korean Geotechical Society Conference
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• 2001.03a
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• pp.299-306
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• 2001

Crushed Stone Pile(CSP) is one of the ground improvement methods available to loose sand and clayey ground by forming compacted CSP in the weak soil layer. The effects of this method are enhancement of ground bearing capacity, reduction of settlement and prevention of lateral ground movement in cohesive layer, reduction of liquefaction potential in sandy ground. This study performs model tests in 1.0m${\times}$1.0m${\times}$1.0m and 1.5m${\times}$1.5m${\times}$l.2m model tank to observe bearing capacity of CSP treated ground. The area replacement ratio of CSP composite ground varies 20%, 30% and 40% with square grid pattern. After the composite ground was consolidated under pressure of 0.5kg/$\textrm{cm}^2$ and 1.0kg/$\textrm{cm}^2$, load tests were carried out. The results show that ultimate bearing capacity increases with area replacement ratio and the preconsolidation pressure of ground.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.316-319
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• 1998

RPWM(Random Pulse Width Modulation) is a switching technique to spread the voltage and current harmonics on the wide frequency area. Using randomly changed switching frequency of the inverter, the power spectrum of the electromagnetic acoustic noise cab be spread to the wide-band area. The wide-band noise is much more comfortable and less annoying than the narrow-band one. So RPWM have been attracting an interest as an excellent method for the reduction of acoustic noise on the inverter drive system. In this paper a new RPPWM (Random Position PWM) is proposed and implemented. Each of three pulses is located randomly in each switching interval. Along with the randomization of PWM pulses, the space vector modulation is executed in the C167 microcontroller also. The experimental results show that the voltage and current harmonics were spread to wide band area and that the audible switching noise was reduced by proposed RPPWM method.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.04a
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• pp.242-242
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• 2013

Recently, importance of working environment is increased in commercial vessel and offshore structure. Marine facility design and ambient environment condition are influenced to enhancing human performance and reducing human errors. Consequently, the quality of accommodation where offshore facility crews sleep, eat and relax will influence their job performance and overall sense of comport and well-being. Therefore, adequate acoustic isolation between adjacent spaces is normally required to achieve satisfactory internal noise levels, acoustic privacy and speech intelligibility. In this study, the reverberation time is investigated in the public areas where there are not provided the information of material's noise reduction coefficient (NRC). The experiment of reverberation time is rarely performed for the various type public areas in a marine structure. Therefore, the reverberation time in a vessel is investigate in order to evaluate the room's noise reduction coefficient (NRC) in a public area.

• Journal of IKEEE
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• v.19 no.2
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• pp.271-275
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• 2015

This paper proposes a unified HEVC $4{\times}4$ IDCT/IDST architecture for area reduction. In general, $4{\times}4$ IDCT and $4{\times}4$ IDST blocks are implemented separately, and they are connected with multiplexers. In the proposed arechitecture, these two blocks are unified, and internal hardware resources such as multipliers are shared. This reduces the chip area. The synthesized block in 0.18 um technology is 2,795 gates, and the gate count is reduced by 9.44% in comparison with conventional designs.