• Title/Summary/Keyword: approximation technique

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Modeling of functional surface using Polynomial Regression (다항식회귀분석을 이용한 기능성곡면의 모델링)

  • 윤상환;황종대;정윤교
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2002.10a
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    • pp.376-380
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    • 2002
  • This research presents modeling of a functional surface which is a constructed free-formed surface. The modeling introduced in this paper adopts polynomial regression that is utilizing approximating technique. The measured data are obtained from measuring with Coordinate Measuring Machine. This paper introduces efficient methods of Reverse Engineering using Polynomial Regression.

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Optimal Path planning and navigation for an autonomous mobile robot

  • Lee, Jang-Gyu-;Hakyoung-Chung
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1993.06a
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    • pp.1258-1261
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    • 1993
  • This paper presents a methodology of path planning and navigation for an autonomous mobile robot. A fast algorithm using decomposition technique, which computes the optimal paths between all pairs of nodes, is proposed for real-time calculation. The robot is controlled by fuzzy approximation reasoning. Our new methodology has been implemented on a mobile robot. The results show that the robot successfully navigates to its destination following the optimal path.

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Scattering analysis of curved FSS using Floquet harmonics and asymptotic waveform evaluation technique

  • Jeong, Yi-Ru;Hong, Ic-Pyo;Chun, Heoung-Jae;Park, Yong Bae;Kim, Youn-Jae;Yook, Jong-Gwan
    • Steel and Composite Structures
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    • v.17 no.5
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    • pp.561-572
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    • 2014
  • In this paper, we present the scattering characteristics of infinite and finite array using method of moment (MoM) with Floquet harmonics and asymptotic waveform evaluation (AWE) technique. First, infinite cylindrical dipole array is analyzed using the MoM with entire domain basis function and cylindrical Floquet harmonics. To provide the validity of results, we fabricated the cylindrical dipole array and measured the transmission characteristics. The results show good agreements. Second, we analyzed the scattering characteristics of finite array. A large simulation time is needed to obtain the scattering characteristics of finite array over wide frequency range because Floquet harmonics can't be applied. So, we used the MoM with AWE technique using Taylor series and Pade approximation to overcome the shortcomings of conventional MoM. We calculated the radar cross section (RCS) as scattering characteristics using the proposed method in this paper and the conventional MoM for finite planar slot array, finite spherical slot array, and finite cylindrical dipole array, respectively. The compared results agree well and show that the proposed method in this paper is good for electromagnetic analysis of finite FSS.

A 10-bit 10-MS/s 0.18-um CMOS Asynchronous SAR ADC with Time-domain Comparator (시간-도메인 비교기를 이용하는 10-bit 10-MS/s 0.18-um CMOS 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Hom;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.88-90
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    • 2012
  • This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

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An Analytic Calculation Method for Delay Time of RC-class Interconnects (RC-class 회로 연결선의 지연 시간 계산을 위한 해석적 기법)

  • Kal, Won-Kwang;Kim, Seok-Yoon
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.7
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    • pp.1-9
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    • 1999
  • This paper presents an analytic 3rd order calculation methods, without simulations, for delay time of RC-class circuits which are conveniently used to on-chip interconnects. While the proposed method requires comparable evaluation time than the previous 2nd order calculation method, it ensures more accurate results than those of 2nd order method. The proposed analytic delay calculation method guarantees allowable error tolerances when compared to the results obtained from the AWE (Asymptotic Waveform Evaluation) technique and has better performance in evaluation time as well as numerical stability. The first algorithm of the proposed method requires 8 moments for the 3rd order approximation and yields more accurate delay time approximation. The second algorithm requires 6 moments for the 3rd order approximation and results in shorter evaluation time, the accuracy of which may be less than the first algorithm.

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A Robust Backpropagation Algorithm and It's Application (문자인식을 위한 로버스트 역전파 알고리즘)

  • Oh, Kwang-Sik;Kim, Sang-Min;Lee, Dong-No
    • Journal of the Korean Data and Information Science Society
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    • v.8 no.2
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    • pp.163-171
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    • 1997
  • Function approximation from a set of input-output pairs has numerous applications in scientific and engineering areas. Multilayer feedforward neural networks have been proposed as a good approximator of nonlinear function. The back propagation(BP) algorithm allows multilayer feedforward neural networks to learn input-output mappings from training samples. It iteratively adjusts the network parameters(weights) to minimize the sum of squared approximation errors using a gradient descent technique. However, the mapping acquired through the BP algorithm may be corrupt when errorneous training data we employed. When errorneous traning data are employed, the learned mapping can oscillate badly between data points. In this paper we propose a robust BP learning algorithm that is resistant to the errorneous data and is capable of rejecting gross errors during the approximation process, that is stable under small noise perturbation and robust against gross errors.

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Low Power 31.6 pJ/step Successive Approximation Direct Capacitance-to-Digital Converter (저전력 31.6 pJ/step 축차 근사형 용량-디지털 직접 변환 IC)

  • Ko, Youngwoon;Kim, Hyungsup;Moon, Youngjin;Lee, Byuncheol;Ko, Hyoungho
    • Journal of Sensor Science and Technology
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    • v.27 no.2
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    • pp.93-98
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    • 2018
  • In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC (분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.2
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    • pp.414-422
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    • 2013
  • This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

Virtual Make-up System Using Light and Normal Map Approximation (조명 및 법선벡터 지도 추정을 이용한 사실적인 가상 화장 시스템)

  • Yang, Myung Hyun;Shin, Hyun Joon
    • Journal of the Korea Computer Graphics Society
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    • v.21 no.3
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    • pp.55-61
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    • 2015
  • In this paper, we introduce a method to synthesize realistic make-up effects on input images efficiently. In particular, we focus on shading on the make-up effects due to the lighting and face curvature. By doing this, we can synthesize a wider range of effects realistically than the previous methods. To do this, the information about lighting information together with the normal vectors on all pixels over the face region in the input image. Since the previous methods that compute lighting information and normal vectors require relatively heavy computation cost, we introduce an approach to approximate lighting information using cascade pose regression process and normal vectors by transforming, rendering, and warping a standard 3D face model. The proposed method consumes much less computation time than the previous methods. In our experiment, we show the proposed approximation technique can produce naturally looking virtual make-up effects.

A Two-Step Vertex Selection Method for Minimizing Polygonal Approximation Error (다각형 근사 오차를 최소화하기 위한 2단계 정점 선택 기법)

  • 윤병주;이훈철;고윤호;이시웅;김성대
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.40 no.6
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    • pp.114-123
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    • 2003
  • The current paper proposes a new vertex selection scheme for polygon-based contour coding. To efficiently characterize the shape of an object, we incorporate the curvature information in addition to the conventional maximum distance criterion in vertex selection process. The proposed method consists of "two-step procedure." At first, contour pixels of high curvature value are selected as key vortices based on the curvature scale space (CSS), thereby dividing an overall contour into several contour-segments. Each segment is considered as an open contour whose end points are two consecutive key vortices and is processed independently. In the second step, vertices for each contour segment are selected using progressive vertex selection (PVS) method in order to obtain minimum number of vertices under the given maximum distance criterion ( $D_{max}$$^{*}$). Furthermore, the obtained vortices are adjusted using the dynamic programming (DP) technique to optimal positions in the error area sense. Experimental results are presented to compare the approximation performances of the proposed and conventional methods.imation performances of the proposed and conventional methods.