• 한국전기전자재료학회논문지
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• 제17권1호
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• pp.7-15
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• 2004

The ferroelectric SBT thin films as a material of capacitors for non-volatile FRAMs have some problems that its remanent polarization value is relatively low and the crystallization temperature is quite high abovc 80$0^{\circ}C$. Therefore, in this paper, SBTN solution with S $r_{0.9}$B $i_{2.1}$T $a_{1.8}$N $b_{0.2}$$O_{9}$ composition was synthesized by sol-gel method. Sr(O $C_2$ $H_{5}$)$_2$, Bi(TMHD)$_3$, Ta(O $C_2$ $H_{5}$)$_{5}$and Nb(O $C_2$ $H_{5}$)$_{5}$ were used as precursors, which were dissolved in 2-methoxyethanol. SBTN thin films with 200 nm thickness were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. UV-irradiation in a power of 200 W for 10 min and rapid thermal annealing in a 5-Torr-oxygen ambient at 76$0^{\circ}C$ for 60 sec were used to promote crystallization. The films were well crystallized and fine-grained after annealing at $650^{\circ}C$ in oxygen ambient. The electrical characteristics of 2Pr=11.94 $\mu$C/$\textrm{cm}^2$, Ps＋/Pr＋=0.54 at the applied voltage of 5 V were obtained for a 200-nm-thick SBTN films. This results show that 2Pr values of the UV irradiated and rapid thermal annealed SBTN thin films at the applied voltage of 5 V were about 57% higher than those of no additional processed SBTN thin films. thin films.lms.s.s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 공업화학
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• 제17권5호
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• pp.471-475
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• 2006

$VO_x$ 박막이 상온에서 $Pt/Ti/SiO_{2}/Si$ 기판위에 반응성 radio frequency (rf) 마그네트론 스퍼터링 방법에 의하여 450 nm 두께로 증착되었다. 증착 공정에서 산소의 농도와 타겟에 인가되는 rf power를 변수로 설정하여 증착 속도를 조사하였다. $VO_x$ 박막의 증착속도는 산소 농도가 증가함에 따라서 감소하고, rf power가 증가할수록 증가하는 것이 관찰되었다. 증착된 $VO_x$ 박막은 $O_{2}$와 $N_{2}$ 가스 분위기에서 $450^{\circ}C$의 온도로 2, 4, 그리고 6 h 동안 각각 열처리 되었고, 열처리 과정을 진행한 후 x-ray diffraction (XRD) 분석을 이용하여 열처리 전과 후의 결정성 변화를 관찰하였다. 그리고 열처리 전과 후의 $VO_x$ 박막의 표면과 단면을 field emission scanning electron microscopy (FESEM)를 이용하여 관찰하였으며 전류-전압 측정을 이용하여, 증착된 $VO_x$ 박막의 metal-insulator transition (MIT) 특성을 관찰하였다. $N_{2}$ 분위기에서 열처리된 $VO_x$ 박막보다 $O_{2}$ 분위기에서 열처리된 $VO_x$ 박막에서 더 우수한 MIT 특성을 관찰 할 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 추계학술대회 논문집 전기물성,응용부문
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• pp.23-25
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• 2001

In this work, the $Ta_2O_5$ thin films were deposited on Pt/n-Si substrate by reactive magnetron sputtering and the RTA treatment at temperatures range from 650 to $750^{\circ}C$ in $O_2$ and vacuum. X-ray diffraction analysis, FE SEM, dielectric properties and leakage current density have been used to study the structural and electrical properties of the $Ta_2O_5$ thin films. XRD result showed that as- deposited films were amorphous and the annealed films crystallized (<$700^{\circ}C$) into ${\beta}-Ta_2O_5$. The crystallinity increased with temperature in terms of an increase in the intensity of the diffracted peaks(${\beta}-Ta_2O_5$) and annealing in oxygen reduced defect dang1ing Ta-O bonds. As deposited $Ta_2O_5$ films show the leakage current density $10^{-7}$ to $10^{-8}$ (A/$cm^2)$ at low electric fields (<200 kV/cm) However, it was found leakage current density of $Ta_2O_5$ thin films decreased with $O_2$ ambient annealing. The dielectric constant of the as deposited $Ta_2O_5$ thin films was ${\varepsilon}_r$ $9{\sim}11$ but the dielectric constant was increased after RTA treatment in $O_2$ ambient more then in vacuum.

• 마이크로전자및패키징학회지
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• 제10권4호
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• pp.29-33
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• 2003

n-형 탄화규소 반도체에 대한 구리금속을 이용하여 오옴성 접촉 구조를 제작하였다. 제작된 구리접촉에 대해 후속열처리 조건과 금속접촉 구조에 따른 재료적, 전기적 성질의 변화를 조사하였다. 금속접촉의 오옴성 성질은 금속박막의 구조 뿐 아니라 열처리조건에 대해서도 크게 좌우됨을 알 수 있었다. 열처리는 급속열처리 장치를 이용한 진공상태 및 환원 분위기에서 2단계 열처리방식을 통하여 시행하였다. 접촉비저항의 측정을 위해 TLM 구조를 만들었으며 면저항 ($R_{s}$), 접합저항 ($R_{c}$), 이동거리 ($L_{T}$), 패드간거리 (d), 전체저항 ($R_{T}$) 값을 구하여 알려진 계산식에 의해 접촉비저항 ($p_{c}$) 값을 추정하였다. 진공보다 환원분위기에서 후속 열처리를 수행한 시편이 양호한 전기적 성질을 가짐을 알 수 있었다. 가장 양호한 결과는 Cu/Si/Cu 구조를 가진 금속접촉 결과이었으며 접촉비저항 ($p_{c}$)은 $1.2\times 10^{-6} \Omega \textrm{cm}^2$의 낮은 값을 얻을 수 있었다. 재료적 성질은 XRD를 이용하여 분석하였고 SiC 계면 상에 구리와 실리콘이 결합한 구리 실리사이드가 형성됨을 알 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.157-157
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• 2010

Vertical-structure light-emitting diodes (V-LEDs) by laser lift-off (LLO) have been exploited for high-efficiency GaN-based LEDs of solid-state lightings. In V-LEDs, emitted light from active regions is reflected-up from reflective ohmic contacts on p-GaN. Therefore, silver (Ag) is very suitable for reflective contacts due to its high reflectance (>95%) and surface plasmon coupling to visible light emissions. In addition, low contact resistivity has been obtained from Ag-based ohmic contacts annealed in oxygen ambient. However, annealing in oxygen ambient causes Ag to be oxidized and/or agglomerated, leading to degradation in both electrical and optical properties. Therefore, preventing Ag from oxidation and/or agglomeration is a key aspect for high-performance V-LEDs. In this work, we demonstrate the enhanced thermal stability of Ag-based Ohmic contact to p-GaN by reducing the thermal compressive stress. The thermal compressive stress due to the large difference in CTE between GaN ($5.6{\times}10^{-6}/^{\circ}C$) and Ag ($18.9{\times}10^{-6}/^{\circ}C$) accelerate the diffusion of Ag atoms, leading to Ag agglomeration. Therefore, by increasing the additional residual tensile stress in Ag film, the thermal compressive stress could be reduced, resulting in the enhancement of Ag agglomeration resistance. We employ the thin Ni layer in Ag film to form Ni/Ag mutli-layer structure, because the lattice constant of NiO ($4.176\;{\AA}$ is larger than that of Ag ($4.086\;{\AA}$). High-resolution symmetric and asymmetric X-ray diffraction was used to measure the in-plane strain of Ag films. Due to the expansion of lattice constant by oxidation of Ni into NiO layer, Ag layer in Ni/Ag multi-layer structure was tensilely strained after annealing. Based on experimental results, it could be concluded that the reduction of thermal compressive stress by additional tensile stress in Ag film plays a critical role to enhance the thermal stability of Ag-based Ohmic contact to p-GaN.

• 분석과학
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• 제6권2호
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• pp.217-223
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• 1993

저항가열식 진공중착기를 이용하여 실온(ambient temp.)과 $250^{\circ}C$에서 알루미나 기판 위에 Au/Cr, Au/Ni/Cr 및 Au/Pd/Cr 박막을 제조하였으며, 공기 중에서 $300^{\circ}C$, $450^{\circ}C$, $600^{\circ}C$의 온도로 각각 1시간 동안 열처리하였다. Au, Ni(또는 Pd) 및 Cr 박막의 두께는 각각 $1000{\AA}$, $300{\AA}$, 및 $50{\AA}$이었다. 박막 제조시 기판의 온도와 박막 제조 후 열처리 온도는 각 층의 상호확산으로 인하여 박막의 면저항값에 영향을 주었다. Auger depth profile 분석결과, Au/Cr 시스템에서는 기판의 온도는 $250^{\circ}C$로 하여 박막을 제조할 때 이미 Cr은 Au 표면으로 확산되었으며, 열처리 후에는 Au의 분포도만 변화하였다. Au/Ni/Cr과 Au/Pd/Cr 시스템의 경우 Ni와 Pd 모두 확산현상이 발견되었으며, 특히 Ni(약 45 at.%)는 Au 박막 표면으로 확산되어 산화되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.764-768
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• 2002

Characteristics of ohmic Co/Si/Co contacts to n-type 4H-SiC are investigated systematically. The ohmic contacts were formed by annealing Co/Si/Co sputtered sequentially. The annealings were performed at $800^{\circ}C$ using RTP in vacuum ambient and $Ar:H_2$(9:1) ambient, respectively. The specific contact resistivity$(\rho_c)$, sheet resistance$(R_s)$, contact resistance$(R_c)$, transfer length$(L_T)$ were calculated from resistance$(R_T)$ versus contact spacing(d) measurements obtained from TLM(transmission line method) structure. While the resulting measurement values of sample annealed at vacuum ambient were $\rho_c=1.0{\tiimes}10^{-5}{\Omega}cm^2$, $R_c=20{\Omega}$ and $L_T$ = 6.0 those of sample annealed at $Ar:H_2$(9:1) ambient were $\rho_c=4.0{\tiimes}10^{-6}{\Omega}cm^2$, $R_c=4.0{\Omega}$ and $L_T$ = 2.0. The physical properties of contacts were examined using XRD and AES. The results showed that cobalt silicide was formed on SiC and Co was migrated into SiC.

• 한국재료학회지
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• 제14권10호
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• pp.688-695
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• 2004

The capacitor contact barrier(CCB) layers have been introduced in the FeRAM integration to prevent the Pt/Al reaction during the back-end processes. Therefore, the interdiffusion and intermetallic formation in $Pt(1500{\AA})/Al(3000{\AA})$ film stacks were investigated over the annealing temperature range of $100\sim500^{\circ}C$. The interdiffusion in Pt/Al interface started at $300^{\circ}C$ and the stack was completlely intermixed after annealing over $400^{\circ}C$ in nitrogen ambient for 1 hour. Both XRD and SBM analyses revealed that the Pt/Al interdiffusion formed a single phase of $RtAl_2$ intermetallic compound. On the other hand, in the presence of TiN($1000{\AA}$) barrier layer at the Pt/Al interface, the intermetallic formation was completely suppressed even after the annealing at $500^{\circ}C$. These were in good agreement with the predicted effect of the TiN diffusion barrier layer. But the conventional TiN CCB layer could not perfectly block the Pt/Al reaction during the back-end processes of the FeRAM integration with the maximum annealing temperature of $420^{\circ}C$. The difference in the TiN barrier properties could be explained by the voids generated on the Pt electrode surface during the integration. The voids were acted as the starting point of the Pt/Al reaction in real FeRAM structure.