• 반도체디스플레이기술학회지
• /
• 제10권1호
• /
• pp.101-105
• /
• 2011

In case of high-tech process industries such as semiconductor and TFT-LCD manufactures, fault of a virtually finished product that is value-added one, since it has gone throughout the most of processes, may give rise to quality cost nearly amount to its selling price and can be a main cause that decreases the efficiency of manufacturing process. This paper proposes a real-time dispatching algorithm for semiconductor manufacturing process with rework. In order to evaluate the proposed algorithm, this paper examines the performance of the proposed method by comparing it with that of the existing dispatching algorithms, based on various experimental data.

• 반도체디스플레이기술학회지
• /
• 제21권1호
• /
• pp.62-66
• /
• 2022

Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The packaging process is the final step in wafer manufacturing. Problems in the wafer packaging process cause large losses. The vibrations are supposed to be the most important factors for the packaging quality. In this study, the structure of a packaging box was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.

• 한국IT서비스학회지
• /
• 제8권4호
• /
• pp.165-174
• /
• 2009

This paper outlines opportunities and challenges in the implementation of BPEL based WFMS(WorkFlow Management System) for the MES(Manufacturing Execution Systems) in semiconductor manufacturing. At present, the most MESs in semiconductor wafer fabrication shop have the problems in terms of application software integration, reactivity, and adaptability. When a plant has to produce new product mix, remodel the manufacturing execution process, or replace obsolete equipments, the principal road blocks for responding to new manufacturing environment are the difficulties in porting existing application software to new configurations. In this paper, the issues about WFMS technologies including BPEL standard applied for MES are presented. And then, we introduce the integrated development framework named nanoFlow which is optimized for developing the BPEL based WFMS application for automated manufacturing system. And we describe a WFMS implemented with using nanoFlow framework, review and evaluate the system.

• 반도체디스플레이기술학회지
• /
• 제16권1호
• /
• pp.29-33
• /
• 2017

This paper presents a development of vision aligner with three channels for the wafer and plate bonding machine in manufacturing of LED. The developed vision aligner consists of three cameras and performs wafer alignment of rotation and translation, flipped wafer detection, and UV Tape detection on the target wafer and plate. Normally the process step of wafer bonding is not defined by standards in semiconductor's manufacturing which steps are used depends on the wafer types so, a lot of processing steps has many unexpected problems by the workers and environment of manufacturing such as the above mentioned. For the mass production, the machine operation related to production time and worker's safety so the operation process should be operated at one time with considering of unexpected problem. The developed system solved the 4 kinds of unexpected problems and it will apply on the massproduction environment.

• 대한산업공학회지
• /
• 제40권2호
• /
• pp.215-222
• /
• 2014

This paper provides a real-time loading strategy for batch processing machines in which a number of jobs are simultaneously processed as a batch. The batch processing machines can be seen in both manufacturing industries (e.g., semiconductor, automobile and metal working) and service industries (transportation vehicles, mail shipment and theme park). This paper focuses on batch processing machines in semiconductor manufacturing. We present a look-ahead loading strategy for tardiness minimization where future arrivals and due dates are taken into consideration. Simulation tests are performed on the presented strategy and some existing loading heuristics under various production settings with different traffic intensities and forecasting errors. Experimental results show that our strategy provides the performance of good quality.

• 대한산업공학회지
• /
• 제22권2호
• /
• pp.231-245
• /
• 1996

Semiconductor manufacturing line includes several batch processes which are to be controlled effectively to enhance the productivity of the line. The key problem in batch processes is a dynamic batch sizing problem which determines number of lots processed simultaneously in a single botch. The batch sizing problem in semiconductor manufacturing has to consider delay of lots, setup cost of the process, machine utilization and so on. However, an optimal solution cannot be attainable due to dynamic arrival pattern of lots, and difficulties in forecasting future arrival times of lots of the process. This paper proposes an efficient batch sizing heuristic, which considers delay cost, setup cost, and effect of the forecast errors in determining the botch size dynamically. Extensive numerical experiments through simulation are carried out to investigate the effectiveness of the proposed heuristic in four key performance criteria: average delay, variance of delay, overage lot size and total cost. The results show that the proposed heuristic works effectively and efficiently.

• 반도체디스플레이기술학회지
• /
• 제5권4호
• /
• pp.17-22
• /
• 2006

In the manufacturing processes of semiconductor, test process is important for quality of products. In the manufacturing process of dynamic memory, memory test is more important. So, automatic test equipment(ATE) is used necessarily. But, according to increase of speed of dynamic memory operation, the rapid test equipment is needed. Impedance matching between ATE and dynamic memory is expected to be an important problem for making a rapid test equipment over 1Gbps. According to increase of speed, inner impedance of ATE also works on important parameter for test. This paper is about the method that is for impedance matching of inner impedance and coaxial cable occurring in manufacturing of ATE. We proved effects of inner impedance by electric theory and verified the method of impedance matching using computer simulation.

• 한국정밀공학회지
• /
• 제15권10호
• /
• pp.103-112
• /
• 1998

The evolution of semiconductor manufacturing technology has accelerated the reduction of device dimensions and the increase of integrated circuit density. In order to improve yield within a short turn around time and maintain it at high level, a system that can rapidly determine problematic processing steps is needed. The statistical process control detects abnormal process variation of key parameters. Expert systems in SPC can serve as a valuable tool to automate the analysis and interpretation of control charts. A set of IF-THEN rules was used to formalize knowledge base of special causes. This research proposes a strategy to apply expert system to SPC in semiconductor manufacturing. In analysis, the expert system accomplishes the instability detection of process parameter, In diagnosis, an engineer is supported by process analyzer program. An example has been used to demonstrate the expert system and the process analyzer.

• 전기학회논문지
• /
• 제61권9호
• /
• pp.1330-1335
• /
• 2012

This paper proposes an automatic measurement sampling method for the semiconductor manufacturing process. The method recommends sampling rates using information of process capability indexes and production scheduling plan within the restricted metrology capacity. In addition, it automatically controls the measurement WIP (Work In Process) using measurement priority values to minimize the measurement risks and optimize the measurement capacity. The proposed sampling method minimizes measurement controls in the semiconductor manufacturing process and improves the fabrication productivity via reducing measurement TAT (Turn Around Time), while guaranteeing the level of process quality.

• 센서학회지
• /
• 제8권1호
• /
• pp.38-44
• /
• 1999

본 논문에서는 8빔 압저항형 가속도센서에서 하나 이상의 빔이 파손되는 대부분의 경우에 대하여 에러신호를 검출할 수 있는 자기진단회로를 구현하고, 이를 PSPICE를 사용하여 시뮬레이션으로 그 기능을 확인하였다. 또한 현재 상용으로 나오는 KA 324 증폭기의 레이아웃을 사용하여 자기진단회로를 표준 바이폴라(bipolar)공정을 이용하여 IC칩으로 제조하고, 24핀 플라스틱 패키지 한 후 자기진단 특성을 조사하였다. 이때, 측정된 회로의 자기진단 특성을 시뮬레이션 결과와 비교하였다.