• The Journal of the Korea institute of electronic communication sciences
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• v.1 no.1
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• pp.8-19
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• 2006

The RF Module which can be adjusted for a digital terrestrial and multi standard(DVB-C, ISDB-T, DVB-H) reception is developed. The Module by single conversion does divide a broadband(45MHz~860MHz) broadcasting channels into three-bands(UHF, VHF_HIGH, VHF_LOW) to satisfy some electrical performances such as image signal rejection, phase noise, IF flatness etc and digital reception specifications such as analog and digital adjacent channel protection, co-channel protection which is important in environment with co-existence both analog and digital broadcasting systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.345-355
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• 2006

The RF Module which can be adjusted for a digital terrestrial and multi standard(DVB-C, ISDB-T, DVB-H) reception is developed. The Module by single conversion does divide a broadband($45MHz{\sim}860MHz$) broadcasting channels into three-bands(UHF, VHF_HIGH, VHF_LOW) to satisfy some electrical performances such as image signal rejection, phase noise, IF flatness etc and digital reception specifications such as analog and digital adjacent channel protection, co-channel protection which is important in environment with co-existence both analog and digital broadcasting systems.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.4
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• pp.397-402
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• 2003

This paper concerns a pulse-width-modulation (PWM) controller design technique using digital redesign. Digital redesign is to convert a well-designed analog controller into an equivalent pulse-amplitude-modulation (PAM) controller maintaining the original analog control system in the sense of state-matching. In similar line of conversion concept, the redesigned PAM controller is converted into a PWM controller using the equivalent area principle. To convincingly visualize the proposed technique, an computer simulation example-attitude control of artificial satellite system is included.

• Journal of Convergence for Information Technology
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• v.11 no.8
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• pp.1-7
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• 2021

In this paper, a method of extending 1 bit by adding an external device to a parallel interface type Digital-to-Analog conversion(D/A C) circuit is presented. To do this, the principle of the D/A C circuit was examined, and the problems that occur when extending one bit by adding individual devices were analyzed, and a bit extension method of the D/A devices using an OP-Amp. circuit was presented. As the proposed method uses the high-precision characteristics of the OP-Amp., even if an error occurs in the device, only the overall size of the output waveform is affected, and the voltage reversal phenomenon that occurs between each bit does not occur. In order to confirm the effect of the proposed method, an experimental circuit was constructed and the absolute voltage of the output and the relative error were measured. As a result, a voltage error of 0.0756% appeared, confirming that the 0.195% requirement for one bit expansion by adding individual devices was sufficiently satisfied.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.129-140
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• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• Proceedings of the Korean Printing Society Conference
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• 2000.12b
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• pp.17-28
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• 2000

Recently, as the prepress mainstream is changed to the digital workflow, various digital proofing systems such as high price dye sublimation printers and low price ink jet printers are widely used in printing industry. However, most of the digital proofing devices have lower resolutions than analog proofing systems and differ with actual color presses in the color gamuts. Therefore, proper color compensations are needed for digital color proofing in order to match color between the proofs and the press sheets. In this paper, we used 3-dimensional look-up table(LUT) and tetrahedral interpolation method for the color space conversion between the device independent color space(CIEXYZ or Lab) and the device dependent color space(CMY) to reduce the color differences between the original copy and digital color proofs and the press sheets.

• Journal of Engineering Education Research
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• v.15 no.4
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• pp.35-40
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• 2012

This study presents an analysis of the current situation (management, approach, adjustment, transportation, and others) of teaching portfolio by examining the teaching portfolio managers (staffs, researchers, teaching assistants, etc.) of 6 universities in the southeast of Korea. The rationale for the study focus is that the existing teaching portfolio either suffers a problem in the transportation, approach, adjustment and/or management or is likely to raise a problem in the future. In order to solve this problem, this study builds a web-based e-teaching portfolio. According to the analysis results, the engineering education system was established in all 6 universities (Ed- note that '6 universities' has already been specified as the study sample). The teaching portfolio was partially digitalized in this system, despite some problems of converting analog data into digital data, which induced difficulties in constructing the overall e-teaching portfolio. Therefore, this study focused on constructing an e-teaching portfolio without developing any additional system by using the existing system positively, and also on determining the appropriate components among the existing teaching portfolio components. Accordingly, in order to convert the analog data into the digital data required for this study, we used a digital camera as the conversion device and converted the teaching portfolio components into those appropriate for the e-teaching portfolio. Finally, we constructed an existing system appropriate for the e-teaching portfolio by using these devices and components.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.256-261
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• 2011

In this paper, a design and an implementation of an Analog to Digital (A/D) converter are introduced for the conversion of monitored battery cell voltage in the cell voltage monitoring(CVM) system in battery management system(BMS), which is one of the key devices of ECO hybrid cars. The A/D converter in CVM system required a middle conversion speed and a high resolution, therefore, a successive approximate register(SAR) typed A/D converter with 10 bits resolution has been designed and implemented using Magna 0.6um 40V process. The measurement result which kept ${\pm}1$ LSB accuracy in the full scale range(FSR) of 5V, showed the usefulness of the SAR typed A/D converter in realizing a CVM system.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.165-169
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• 2008

Analog-to-Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal-to-quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.800-807
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• 2006

To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in $0.25{\mu}m$ CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is $0.50\;x\;0.35mm^{2}$. The averaged power consumption is 1.7 mW.