• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.2
• /
• pp.134-139
• /
• 2004

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of pre-amplifiers, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.8
• /
• pp.740-747
• /
• 2015

Recently, mobile communication systems using the millimeter-wave frequency band have been proposed, and the importance of efficient compensation of the nonlinearity caused by 60 GHz high-power amplifiers(HPAs) is increasing. In this paper, we propose a predistorter structure based on multiple coefficient sets which are separately used to different ranges of input power values. These ranges correspond to varying levels of nonlinearity characteristics. The structure is applied to the 60 GHz HPA FMM5715X and the performance of correcting the nonlinearity of LTE signals is evaluated. Evaluation results using a hardware testbed demonstrate that the proposed predistorter structure achieves the maximum of 6 dB gain over the conventional method in terms of the adjacent channel leakage ratio(ACLR).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.1
• /
• pp.92-95
• /
• 2016

In this paper, an UHF-band 1 kW solid-state pulsed power amplifier was designed and implemented for the thermoacoustic imaging(TAI) at 900 MHz. The designed power amplifier has a pulse width of $80{\mu}s$ and a duty cycle of 1 % for short-pulse operation. The overall amplifier was implemented by combining of 16 single-power amplifiers adopting MRFE6P9220HR3 LDMOSFET using wilkinson power dividers. The solid-state pulsed power amplifier shows 25 % drain efficiency with a gain of 76.2 dB when the output power is 60.2 dBm for a -16 dBm input power at center frequency.

• Korean Journal of Optics and Photonics
• /
• v.19 no.1
• /
• pp.60-67
• /
• 2008

An all-optical 4-bit Gray code to binary coded decimal (BCD) converter by means of commercially available numerical analysis tool (VPI) was demonstrated, for the first time to our knowledge. Circuit design approach was modified appropriately in order to fit the electrical method on an all-optical logic circuit based on a cross gain modulation (XGM) process so that signal degradation due to the non-ideal optical logic gates can be minimized. Without regenerations, Q-factor of around 4 was obtained for the most severely degraded output bit (least significant bit-LSB) with 2.5 Gbps clean input signals having 20 dB extinction ratio. While modifying the two-level simplification method and Karnaugh map method to design a Gray code to BCD converter, a general design concept was also founded (one-level simplification) in this research, not only for the Gray code to BCD converter but also for any general applications.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.6
• /
• pp.436-445
• /
• 2001

In this paper, we introduce modulo ( 2$^n$-1) parallel-processing residue multipliers, using Op Amp circuits, and their technological application to designing binary multipliers. The limit of multiplying speed in computational processing is a serious harrier in the advances of VLSI technology. To solve this problem, we implement a class of modulo ( 2$^n$-1) parallel multipliers having superior time complexity to O( log$_2$( log$_2$( log$_2$$^n$))) by applying Op Amp circuits, while investigating their technological application to binary multipliers. Since they have excellent time & area complexity compared with previous parallel multipliers, and are applicable to designing binary multipliers of the same efficiency, such parallel multipliers possess high academic value. Indexing Terms Modular Multipliers. Binary Multipliers. Parallel Processing, Operational Amplifiers, Mersenne Numbers.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.8
• /
• pp.62-67
• /
• 1999

In this letter, a scheme for increasing the input power dynamic range of wavelength converters based on cross-gain modulation (XGM) in semiconductor optical amplifiers (SOA/s) is proposed. We investigate the effect of input pump and probe powers on the power penalty, the measure of performance for the wavelength converters. As a result, we show that the optimal bit error rate (BER) performance can be obtained when the probe power is kept 3 dB weaker than the pump power. Using this characteristic, we propose the wavelength converter scheme that controls the probe power level by monitoring the input pump power and adjusting the bias current of probe source accordingly. Consequently, the wavelength converter for wide input power dynamic range can be implemented. We show that an input power dynamic range of more than 20 dB at 2.5 Gb/s is achievable.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.2
• /
• pp.141-146
• /
• 2009

In this paper, a novel harmonic control circuit has been proposed for the design of high-efficiency power amplifier with Si LDMOSFET. The proposed harmonic control circuit haying the short impedances for the second- and third-harmonic components has been used to design the in/output matching network. The efficiency enhancement effect of the proposed harmonic control circuit is superior to the class-F or inverse class-F harmonic control circuit. Also, when the proposed harmonic control circuit has been adapted to the input matching network as well as the output matching network, the of ficiency enhancement effect of the proposed power amplifier has increased all the more. The measured maximum power added efficiency (PAE) of the proposed power amplifier is 82.68% at 1.71GHz band. Compared with class-F and inverse class-F amplifiers, the measured maximum PAE of the proposed power amplifier has increased in $5.08{\sim}9.91%$.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.10
• /
• pp.8-16
• /
• 2010

An orthogonal frequency division multiplexing (OFDM) system is a special case of multicarrier transmission, where a single data stream is transmitted over a number of lower-rate subcarriers. One of the main reasons to use OFDM is to increase robustness against frequency-selective fading or narrowband interference. However, in the radio systems the distortion introduced by high power amplifiers (HPA's) such as traveling wave tube amplifier (TWTA) considered in this paper, is also critical. Since the signal amplitude of the OFDM system is Rayleigh-distributed, the performance of the OFDM system is significantly degraded by the nonlinearity of the HPA in the OFDM transmitter. In this paper, we propose a simplicial canonical piecewise-linear (SCPWL) model based digital predistorter to compensate for nonlinear distortion introduced by an HPA in an OFDM system. Computer simulation is carried on an OFDM system under additive white Gaussian noise (AWGN) channels with 16-QAM and 64-QAM modulation schemes and modulator/demodulator implemented with 1024-point FFT/IFFT. The simulation results demonstrate that the proposed predistorter achieves significant performance improvement by effectively compensating for the nonlinearity introduced by the HPA.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.82-90
• /
• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.339-345
• /
• 2016

This paper presents a two-stage power amplifier MMIC using a $0.4{\mu}m$ GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of $2.0{\times}1.9mm^2$ and was mounted on a $4{\times}4$ QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.