• E2M - 전기 전자와 첨단 소재
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• 제10권8호
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• pp.813-818
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• 1997

In this study the thin film air core and magnetic core inductors consisting of planar coil and/or CoNbZr amorphous magnetic layers on a Si substrate were fabricated as spiral type by using rf magnetron sputtering and wet etching methods. The etchant solution was achieved by iron chloride solution(17.5 mol%) mixed with HF (20 mol%) during 150 sec which etched Cu films and CoNbZr/Cu/CoNbZr multi-layer films. They were about 10${\mu}{\textrm}{m}$ of thickness and 10$\times$10 mm$^2$of size. The properties of thin film magnetic core inductor were 400 nH of Q value at 10 MHz and the resonance frequency was about 300 MHz.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.171-171
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• 2012

Neutral beam assisted chemical vapor deposition (NBa-CVD) process has been developed as a nove,l room temperature deposition process for the light-soaking free nano-crystalline silicon (nc-Si) thin films including intrinsic and n-type doped thin film. During formation of nc-Si thin films by the NBa-CVD process with silicon reflector at room temperature, the energetic particles enhance doping efficiency and crystalline phase in nc-Si thin films without additional heating at substrate. The effects of incident NB energy controlled by the reflector bias have been confirmed by Raman spectra analysis. Additionally, TEM images show uniform nc-Si grains which imbedded amorphous phase without incubation layer. The nc-Si films by the NBa-CVD are hardly degenerated by light soaking; the degradations of photoconductivity were just a few percents before and after light irradiation.

• E2M - 전기 전자와 첨단 소재
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• 제9권3호
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• pp.277-283
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• 1996

The temperature dependent characteristics of hydrogenerated amorphous silcon thin film transistor (a-Si:H TFT) with a bottom gate of N-Type <100> Si wafer were investigated. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the gate voltage increased and decreased with the small gate voltage. According to the variation of gate voltages, drain current of TFT increased by temperature increase, and hysteresis characteristics mainly depended on the temperature increase. The hysteresis current showed negative characteristics curve over 383K. The hysteresis occurance area and the differences of forward and reverse sweep were increased at the higher temperature. Hysteresis current of I$_{d}$(on/off) ratio decreased at the lower temperature and increased at the higher temperature.e.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.252-252
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• 2011

최근 주목받고 있는 amorphous gallium-indium-zinc-oxide (a-GIZO) thin film transistors (TFTs)는 수소가 첨가된 비정질 실리콘 TFT에 비해 높은 이동도와 뛰어난 전기적, 광학적 특성에 의해 큰 주목을 받고 있다. 또한 넓은 밴드갭을 가지므로 가시광 영역에서 투명한 특성을 보이고, 플라스틱 기판 위에서 구부러지는 성질에 의해 플랫 패널 디스플레이나 능동 유기 발광소자 (AM-OLED), 투명 디스플레이에 응용되고 있다. 뿐만 아니라, 일반적인 Poly-Si TFT는 자체적으로 가지는 결정성에 의해 대면적화 시 균일성이 좋지 못하지만 GIZO는 비정질상 이기 때문에 백플레인의 대면적화에 유리하다는 장점이 있다. 이러한 TFT를 제작하기 전, 전기적 특성에 대한 정보를 얻거나 예측하는 것이 중요한데, 이에 따라 고안된 구조가 바로 metal point contact FET (pseudo FET)이다. pseudo FET은 소스/드레인 전극을 따로 증착할 필요 없이 채널을 증착한 후, 프로브 탐침을 채널의 표면에 적당한 압력으로 접촉시켜 전하를 공급하는 소스와 드레인처럼 동작시킬 수 있다. 따라서 소스/드레인을 증착하거나 lithography와 같은 추가적인 공정을 요구하지 않아 소자의 특성을 보다 간단하고 수월하게 분석할 수 있다는 장점이 있다. 본 연구에서는 p-type 기판위에 100nm의 oxidation SiO2를 게이트 절연막으로 사용하는 a-GIZO pseudo FET를 제작하였다. 소자 제작 후, 열처리 온도에 따른 전기적 특성을 분석하였고, 열처리 조건은 30분간 N2 분위기에서 실시하였다. 열처리 후 전기적 특성 분성 결과, 450oC에서 가장 낮은 subthreshold swing 값과 게이트 전압의 더블 스윕 후 문턱 전압의 변화가 거의 없음을 확인하였다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2000년도 추계학술발표회 초록집
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• pp.3-4
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• 2000

Many researchers are interested in the synthesis and characterization of carbon nitride and diamond-like carbon (DLq because they show excellent mechanical properties such as low friction and high wear resistance and excellent electrical properties such as controllable electical resistivity and good field electron emission. We have deposited amorphous carbon nitride (a-C:N) thin films and DLC thin films by shielded arc ion plating (SAIP) and evaluated the structural and tribological properties. The application of appropriate negative bias on substrates is effective to increase the film hardness and wear resistance. This paper reports on the deposition and tribological OLC films in relation to the substrate bias voltage (Vs). films are compared with those of the OLC films. A high purity sintered graphite target was mounted on a cathode as a carbon source. Nitrogen or argon was introduced into a deposition chamber through each mass flow controller. After the initiation of an arc plasma at 60 A and 1 Pa, the target surface was heated and evaporated by the plasma. Carbon atoms and clusters evaporated from the target were ionized partially and reacted with activated nitrogen species, and a carbon nitride film was deposited onto a Si (100) substrate when we used nitrogen as a reactant gas. The surface of the growing film also reacted with activated nitrogen species. Carbon macropartic1es (0.1 -100 maicro-m) evaporated from the target at the same time were not ionized and did not react fully with nitrogen species. These macroparticles interfered with the formation of the carbon nitride film. Therefore we set a shielding plate made of stainless steel between the target and the substrate to trap the macropartic1es. This shielding method is very effective to prepare smooth a-CN films. We, therefore, call this method "shielded arc ion plating (SAIP)". For the deposition of DLC films we used argon instead of nitrogen. Films of about 150 nm in thickness were deposited onto Si substrates. Their structures, chemical compositions and chemical bonding states were analyzed by using X-ray diffraction, Raman spectroscopy, X-ray photoelectron spectroscopy and infrared spectroscopy. Hardness of the films was measured with a nanointender interfaced with an atomic force microscope (AFM). A Berkovich-type diamond tip whose radius was less than 100 nm was used for the measurement. A force-displacement curve of each film was measured at a peak load force of 250 maicro-N. Load, hold and unload times for each indentation were 2.5, 0 and 2.5 s, respectively. Hardness of each film was determined from five force-displacement curves. Wear resistance of the films was analyzed as follows. First, each film surface was scanned with the diamond tip at a constant load force of 20 maicro-N. The tip scanning was repeated 30 times in a 1 urn-square region with 512 lines at a scanning rate of 2 um/ s. After this tip-scanning, the film surface was observed in the AFM mode at a constant force of 5 maicro-N with the same Berkovich-type tip. The hardness of a-CN films was less dependent on Vs. The hardness of the film deposited at Vs=O V in a nitrogen plasma was about 10 GPa and almost similar to that of Si. It slightly increased to 12 - 15 GPa when a bias voltage of -100 - -500 V was applied to the substrate with showing its maximum at Vs=-300 V. The film deposited at Vs=O V was least wear resistant which was consistent with its lowest hardness. The biased films became more wear resistant. Particularly the film deposited at Vs=-300 V showed remarkable wear resistance. Its wear depth was too shallow to be measured with AFM. On the other hand, the DLC film, deposited at Vs=-l00 V in an argon plasma, whose hardness was 35 GPa was obviously worn under the same wear test conditions. The a-C:N films show higher wear resistance than DLC films and are useful for wear resistant coatings on various mechanical and electronic parts.nic parts.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.48-48
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• 2007

P-type transparent conducting $CuGaO_2$ thin films have been prepared by DC/RF sputtering using Quartz(0001) and sapphire(0001) substrates. The target was fabricated by heating a stoichiometric mixture of CuO and $Ga_2O_3$ at 1373K for 12h under $N_2$ atmosphere. The film were deposited under mixture gas of Ar and $O_2(Ar:O_2=4:1)$ during 10~30min. and the as-deposited films were annealed at 1123K and $N_2$ atmosphere. Room temperature conductivity and the activation energy of the sintered body in the temperature range of 223K ~ 423K were 0 004S/cm, 1.9eV, respectively. XRD revealed that all of the as-deposited films were amorphous. Heating of the films deposited on Quartz substrates above 1123K resulted in crystallization with a second phase of $CuSiO_3$, which was assumed owing to reaction with Quartz substrate. The single phase of $CuGaO_2$ was obtained at the film deposited on the sapphire substrates. The transmittance after annealing of DC- and RF-sputtered films were 55~75% at 550nm. From the transmittance and reflectance measurement. the direct band gap of the DC/RF-sputtered films were 3.63eV and 3.57eV. and there was little difference between DC and RF sputtered films.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.390-392
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• 2013

본 논문에서는 투명디스플레이를 구현하기 위해 가장 주목받는 ZnO 계열의 산화물반도체의 특성에 대하여 관찰하였다. 알에프 마그네트론 스퍼터링에 의해 증착된 산화물 반도체의 광학적 특성으로부터 전기적인 신호 동작특성의 상호관계를 알아보았다. 박막내의 결합 혹은 불순물이 증가할수록 PL 특성은 장파장 특성이 우세하게 나타났다. SiOC 박막위에서는 에너지 밴드갭이 증가하면서 단파장 특성이 우세하게 나타났다. 트랜지스터의 특성은 기판의 의존도가 높게 나타났다.

• 전자공학회논문지A
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• 제30A권8호
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• pp.34-41
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• 1993

Effect of high temperature annealing conditions on Ta$_{2}O_{5}$ thin films was investigated. Ta$_{2}O_{5}$ thin films were deposited on P-type silicon substrates by plasma-enhanced chemical vapor deposition (PECVD) using tantalum ethylate. Ta(C$_{2}H_{5}O)_{5}$, and nitrous oxide. N$_{2}$O. The microstructure changed from amorphous to polycrystalline above 700.deg. C annealing temperature. The refractive index, dielectric onstant and leakage current of the film increased as annealing temperature increased. However, annealing in oxygen ambient reduced leakage currents and dielectric constant due to the formation of interfacial SiO$_{2}$ layer. By optimizing annealing temperature and ambient, leakage current lower than 10$^{-8}$ A/cm$^{2}$ and maximum capacitance of 9 fF/${\mu}m^{2}$ could be obtained.

• 한국정보통신학회논문지
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• 제11권6호
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• pp.1099-1103
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• 2007

본 연구는 기존의 방식으로 만든 비정질 실리콘 박막 트랜지스터의 제조공정에서 발생되는 결함에 대한 원인을 분석하고 해결함으로써 수율을 증대시키고 신뢰성을 개선하고자한다. 본 연구의 수소화 된 비정질 실리콘 박막 트랜지스터는 Inverted Staggered 형태로 게이트 전극이 하부에 있다. 실험 방법은 게이트전극, 절연층, 전도층, 에치스토퍼 및 포토레지스터층을 연속 증착한다. 스토퍼층을 게이트 전극의 패턴으로 남기고, 그 위에 n+a-Si:H층 및 NPR(Negative Photo Resister)을 형성시킨다. 상부 게이트 전극과 반대의 패턴으로 NPR층을 패터닝 하여 그것을 마스크로 상부 n+a-Si:H 층을 식각하고, 남아있는 NPR층을 제거한다. 그 위에 Cr층을 증착한 후 패터닝하여 소오스-드레인 전극을 위한 Cr층을 형성시켜 박막 트랜지스터를 제조한다. 이렇게 제조한 박막 트랜지스터에서 생기는 문제는 주로 광식각공정시 PR의 잔존이나 세척시 얇은 화학막이 표면에 남거나 생겨서 발생되며, 이는 소자를 파괴시키는 주된 원인이 된다. 그러므로 이를 개선하기 위하여 ashing이나 세척공정을 보다 엄격하게 수행하였다. 이와 같이 공정에 보다 엄격한 기준의 세척과 여분의 처리 공정을 가하여 수율을 확실히 개선 할 수 있었다.