• 한국자기학회:학술대회 개요집
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• 한국자기학회 1994년도 춘계연구발표회 논문개요집
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• pp.68-69
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• 1994

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2005년도 동계학술연구발표회 및 2차 아시안포럼
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• pp.7-7
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• 2005

• 한국결정성장학회지
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• 제11권4호
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• pp.160-165
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• 2001

The effects of various metals on Field Aided Lateral Crystallization (FALC) behaviors of amorphous silicon (a-Si) were investigated. Under an influence of electric field, metals such s Cu, Ni and Co were found to fasten the lateral crystallization toward a metal-free region, exhibiting a typical FALC behavior while the lateral crystallization of a-Si was not obvious for Pd. However, Au, Al and Cr did not induce the lateral crystallization of a-Si in metal-free region. Such phenomenological differences in various metals were studied in terms of dominant diffusing species (DDS) in the reaction between metal and Si. It was judged that the applied electric field enhanced the crystallization velocity by accelerating the diffusion of metal atoms since the occurrence of lateral crystallization would be strongly dependent on the diffusion of metal atoms than that of Si atoms. Therefore, it was concluded that he only metal-dominant diffusing species in the reaction between metal and Si results in the crystallization of a-Si in metal-free region.

• E2M - 전기 전자와 첨단 소재
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• 제10권8호
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• pp.794-799
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• 1997

Poly-Si films have been prepared by solid phase crystallization of LPCVD(low-pressure CVD) amorphous silicon. The crystallinity of poly-Si films has been derived from UV reflectance spectrum and lies in the range between 70% and 80% . From XRD measurement the peak at 28.2$^{\circ}$from (111) plane is dominantly detected in the SPC poly-Si films, The average grain size of poly-Si film is determined by the image of SEM and varies from 4000 $\AA$ to 8000$\AA$. The electrical conductivity of as-deposited amorphous silicon film is about 2.5$\times$10$^{-7}$ ($\Omega$.cm)$^{-1}$ , and 3~4$\times$10$^{-6}$ ($\Omega$.cm)$^{-1}$ of room temperature conductivity is the SPC poly-Si films. The conductivity activation energies are 0.5~0.6 eV or the 500$\AA$-thick poly-Si films.

• 한국진공학회지
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• 제5권1호
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• pp.73-76
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• 1996

We have prepared hydrogenated amophous silicon (a-si : H) films with superlattice structure by hydrogen radical anneling(HRA) technique. We have studied the preparation of a-Si :H films by HRA and the optical & electronic characteristics. Optical band gap and the hydrogen contents in the a Si : H film is decreased as HRA time increased. We first report a -Si : H film prepared by periodicdeposition of a-Si : H layer and HRA have the superlattice structure using TEM . After 1 hour light soaking on the a-Si :H film prepared by HRA, there are no difference in the temperatre dependence of dark conductivity and the conductivity activation energy. An excellent stability for light in a-Si :H films by HRA can be explained using the long-range structural relaxation of the amorphous network and the propertiesof light -induced defects(LID) proposed by Fritzsche.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.224-225
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• 2007

The Low dielectric properties of epoxy/Annealing $SiO_2$ composites using Annealing new material of nanosized amorphous particles were investigated as function frequency, temperature and filler contents composition. The dielectric constant decrease with increasing frequency and also increase with increasing ambient temperature. The dielectric constant decrease with increase annealing filler contents for epoxy base. The result of x-ray diffraction could obtained single crystal of annealing $SiO_2$ from 500nm amorphous $SiO_2$ powder.

• 한국자기학회지
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• 제16권6호
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• pp.279-282
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• 2006

비정질 강자성 NiFeSiB 자유층을 갖는 자기터널접합 (MTJ)에 대하여 연구하였다. 비정질 자유층이 MTJ의 스위칭 특성에 미치는 영향을 알아보는데 역점을 두어 기존의 CoFe와 NiFe층 대신에 NiFeSiB 자성층을 사용하였다. $Ni_{16}Fe_{62}Si_{8}B_{14}$는 $Co_{90}Fe_{10}$보다 더 낮은 포화자화도 ($M_{s}:\;800\;emu/cm^{3}$) 그리고 $Ni_{80}Fe_{20}$보다 더 높은 이방성 상수 ($K_{u}:\;2700\;erg/cm^{3}$)를 갖는다. $Si/SiO_{2}/Ta$ 45/Ru 9.5/IrMn 10/CoFe $7/AlO_{x}/CoFeSiB\;(t)/Ru\;60\;(nm)$ 구조는 그 자체의 낮은 포화자화도와 높은 일축 이방성을 가짐으로 인하여 보자력($H_{c}$)을 감소시키고 스위칭 각형을 증가시키게 함으로서 MTJ의 스위칭 특성에 유리한 것으로 조사되었다. 더욱이 미소두께(1 nm)의 CoFe층을 터널장벽/NiFeSiB 경계면에 삽입하면 TMR비와 스위칭 각형이 증가하고 개선되었다.

• 한국재료학회지
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• 제12권11호
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• 한국진공학회지
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• 제2권4호
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• pp.468-473
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• 1993

Damages on Si substrate induced by Ar ion implantation and it annealing behavior during rapid thermal annealing were investigated by the cross-sectional TEM (transmissin electron microscopy), RB(Rutherfordbackscattering) spectra an dthermal wave (TW) modulation reflectance methods. Continuous amorphous layer extending to the surface were generated by Ar ion implantation for higher doses than 1 $\times$1015cm-2. The recrystallization of the amorphous layer prodeeded as the annealing temperature increased . However the amorphous /crystal interfacial undulations caused the micro twins and damage clusters. Damage clusters generated by lower doses than 1 $\times$1015 cm-2 disappeared slowly as the annealing temperature increased, but even at 110$0^{\circ}C$ a few damage clusters still remained.

• Transactions on Electrical and Electronic Materials
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• 제18권5호
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• pp.250-252
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• 2017

High-performance full swing logic inverters were fabricated using amorphous 1 wt% Si doped indium-zinc-oxide (a-SIZO) thin films with different channel layer thicknesses. In the inverter configuration, the threshold voltage was adjusted by varying the thickness of the channel layer. The depletion mode (D-mode) device used a TFT with a channel layer thickness of 60 nm as it exhibited the most negative threshold voltage (-1.67 V). Inverters using enhancement mode (E-mode) devices were fabricated using TFTs with channel layer thicknesses of 20 or 40 nm with excellent subthreshold slope (S.S). Both the inverters exhibited high voltage gain values of 30.74 and 28.56, respectively at $V_{DD}=15V$. It was confirmed that the voltage gain can be improved by increasing the S.S value.