• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.378-380
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• 2011

스테레오스코픽(stereoscopic) 3D 비디오 서비스는 기존 2D 와의 호환성을 유지하면서 새로운 3D 비디오 서비스를 제공할 수 있는 것으로, 전송 대역이 제한된 지상파 방송에서 높은 부호화 효율을 갖는 스테레오스코픽 비디오 코덱이 요구된다. 따라서 3D 를 위한 부가영상의 부호화를 위해 H.264/AVC 등을 고려하고 있으며, 또한 부가영상을 비실시간으로 전송하는 비실시간(Non-Real Time: NRT) 3D 서비스도 고려되고 있다. 본 논문에서는 NRT 3D 서비스를 위한 스테레오스코픽 비디오 부호화에 있어서, HEVC 에서 고려중인 적응루프필터(ALF: Adaptive Loop Filter)를 전/후처리 필터로 적용하는 기법을 제시한다. 특히, 부가영상의 후처리에 ALF 를 적용하기 위하여 부호화 과정에 결정되는 CU(Coding Unit) 구조를 이용하는 HEVC 와 달리 H.264/MVC 로 부호화한 부가영상의 매크로블록(MB) 부호화 모드를 이용한 ALF 적용 기법을 제안한다. 부가영상 부호화에 있어서 전처리 및 후처리 과정으로 ALF 를 적용함으로써 최대 약 20.5%의 부가영상의 부호화 성능 향상을 확인하였다.

• ETRI Journal
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• v.30 no.4
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• pp.506-515
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• 2008

The H.264/AVC standard has adopted new coding tools such as intra-prediction, variable block size, motion estimation with quarter-pixel-accuracy, loop filter, and so on. The adoption of these tools enables an H.264/AVC-coded bitstream to have more information than was possible with previous standards. In this paper, we propose an effective spatial error concealment method with low complexity in H.264/AVC intra-frame. From information included in an H.264/AVC-coded bitstream, we use prediction modes of intra-blocks to recover a damaged block. This is because the prediction direction in each prediction mode is highly correlated to the edge direction. We first estimate the edge direction of a damaged block using the prediction modes of the intra-blocks adjacent to a damaged block and classify the area inside the damaged block into edge and flat areas. Our method then recovers pixel values in the edge area using edge-directed interpolation, and recovers pixel values in the flat area using weighted interpolation. Simulation results show that the proposed method yields better video quality than conventional approaches.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.11a
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• pp.15-17
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• 2018

VVC(Versatile Video Coding)는 입력된 영상을 CTU(Coding Tree Unit) 단위로 분할하여 코딩하며, 이를 다시 QTBTT(Quadtree plus binary tree and triple tree)로 분할하고, TU(Transform Unit)도 이와 같은 단위로 분할된다. 따라서 TU의 크기는 $4{\times}4$, $4{\times}8$, $4{\times}16$, $4{\times}32$, $8{\times}4$, $16{\times}4$, $32{\times}4$, $8{\times}8$, $8{\times}16$, $8{\times}32$, $16{\times}8$, $32{\times}8$, $16{\times}16$, $16{\times}32$, $32{\times}16$, $32{\times}32$, $64{\times}64$의 17가지 종류가 있다. 기존의 VVC 참조 Software인 VTM에서는 디블록킹필터와 SAO(Sample Adaptive Offset)로 이루어진 인루프필터를 이용하여 에러를 복원하는데, 본 논문은 TU 크기에 따라서 원본블록과 복원블록의 차이(에러)가 통계적으로 다름을 이용하여 서로 다른 CNN(Convolution Neural Network)을 구축하고 에러를 복원하는 방법으로 VTM의 인루프 필터를 대체한다. 복원영상의 에러를 감소시키기 위하여 TU 블록크기에 따라 DenseNet의 Dense Block기반 CNN을 구성하고, Hyper Parameter와 복잡도의 감소를 위해 네트워크 간에 일부 가중치를 공유하는 모양의 Network를 구성하였다.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.391-396
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• 2013

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1249-1256
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• 2019

In this paper, we propose a new algorithm to remove acoustic feedback and noise in hearing aids. Instead of using the conventional FIR structure, this algorithm is a deep learning algorithm using neural network adaptive prediction filter to improve the feedback and noise reduction performance. The feedback canceller first removes the feedback signal from the microphone signal and then removes the noise using the Wiener filter technique. Noise elimination is to estimate the speech from the speech signal containing noise using the linear prediction model according to the periodicity of the speech signal. In order to ensure stable convergence of two adaptive systems in a loop, coefficient updates of the feedback canceller and noise canceller are separated and converged using the residual error signal generated after the cancellation. In order to verify the performance of the feedback and noise canceller proposed in this study, a simulation program was written and simulated. Experimental results show that the proposed deep learning algorithm improves the signal to feedback ratio(: SFR) of about 10 dB in the feedback canceller and the signal to noise ratio enhancement(: SNRE) of about 3 dB in the noise canceller than the conventional FIR structure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.4
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• pp.67-76
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• 2012

Expanding services and productions for screen content videos recently, necessity of new compression techniques is emerging. The next-generation video coding standard is also considering specified coding tools for screen content videos, but it is still preliminary stage. In this paper, we investigate the characteristics of screen content videos for which we propose the quantization in spatial domain to improve coding efficiency. The proposed method directly employs quantization for residual signal without any transformations. The proposed method also applies adaptive coefficients prediction and in-loop filter for quantized residual signals in spatial domain based on the characteristics of screen content videos. As a results, the proposed method for the random access, the low-delay and the all-intra modes achieve bit-saving about 4.4%, 5.1%. and 4.9%, respectively.