• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.233-236
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• 2005

Phase noise in a phase-locked-loop (PLL) is unwanted and unavoidable. It is a main concern in oscillation system especially PLL. The phase noise is derived in term of power spectrum density by using a reliable phase noise model. There are four noise sources being considered in this paper, which are generated by reference oscillator, voltage controlled oscillator, filter, and main divider. The major concern for this paper is the noise from the filter. Two types of second order low pass filter are used in the PLL system. Applying the mathematical phase noise model, the output noises are compared. The total noise from the passive filter is lower than the active filter at the offset frequency range between 1 Hz to 33 kHz.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.3
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• pp.1-10
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• 1998

A new oscillator configuration is presented and tested for Josephson voltage standard operated at the cryogenic(4.2K) temperature. Features of active devices are investigated in aspects of 1/f noise, output power, and current collapse at low temperature. The output power of oscillator is optimized by a nonlinear design approach called Harmonic Two Signal Method(HTSM). The embedding newworks of the generalized six oscillators with tow loads are derived. A HEMT oscilliator is designed in X-Band for the Josephson voltage standard and tested at room and cryogenic(4.2K) temperatures. Oscillation frequency, output power, C/N ratio, and fequency stability are compared at room and low temperatures.

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.198-206
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• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• ETRI Journal
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• v.33 no.3
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1125-1128
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• 2003

This paper presents the design method of a Colpitts type oscillator with coplanar waveguide(CPW) structures in the range of Ka-band frequency for transmitter and receiver modules. Series short stubs of CPW patterns provide inductances and capacitances in the range of Ka-band which can be expressed as a CLC-$\pi$ equivalent circuit. The experimentation has employed ro4003 substrates as a CPW substrate which has a dielectric constant of 3.38 and a signal and ground space of 100um. A method of momentum simulation for the CPW patterns has performed with an ADS software tool of Hewlett-Packard Corp. Inductance and capacitance circuits of a Colpitts oscillator was interconnected to a MESFET with CPW bend structures of including the input and output impedance matching circuits of the active transistor. Circuit parameters for impedance matching were determined through the network conversion to the equivalent length of CPW transmission lines by using T-network 1 $\pi$-network conversion circuit. A Colpitts oscillator was fabricated on the substrate of a area of 8.5mm x 17.4mm with a MESFET of Fujitsu FMM5704X and CPW series short stubs. The design suggested the possibility of realizing oscillators on a planar surface for the wireless system of tansmitter and receiver modules in the frequency range of 30GHz

• Journal of electromagnetic engineering and science
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• v.15 no.4
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• pp.232-238
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• 2015

This work describes the development of a D-band (110-170 GHz) signal source based on a SiGe BiCMOS technology. This D-band signal source consists of a V-band (50-75 GHz) oscillator, a V-band amplifier, and a D-band frequency doubler. The V-band signal from the oscillator is amplified for power boost, and then the frequency is doubled for D-band signal generation. The V-band oscillator showed an output power of 2.7 dBm at 67.3 GHz. Including a buffer stage, it had a DC power consumption of 145 mW. The peak gain of the V-band amplifier was 10.9 dB, which was achieved at 64.0 GHz and consumed 110 mW of DC power. The active frequency doubler consumed 60 mW for D-band signal generation. The integrated D-band source exhibited a measured output oscillation frequency of 133.2 GHz with an output power of 3.1 dBm and a phase noise of -107.2 dBc/Hz at 10 MHz offset. The chip size is $900{\times}1,890{\mu}m^2$, including RF and DC pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.1
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• pp.94-99
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• 1997

There are several factors that have influence on the phase noise of an oscillator. But one of the major factors is the flicker noise of a transistor, since the phase noise of an oscillator is generated by mixing the carrier with the low frequency noise near the DC having the characteristic of 1/f. In this paper, we have presented a method on reducing the phase noise of an oscillator by using a low-frequency feedback circuit based on an active bias circuit, and have fabricated a DRO for a DBS receiver. Measurement results show that the phase noise is -92 dBc/Hz at the 10 KHz offset frequency, and from these results we have found out that the reduction method is very effective.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.9
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• pp.798-805
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• 2015

This paper proposes Relaxation Oscillator with Random Number Generator to minimize electromagnetic interference (EMI) noise. DC-DC Converter with Relaxation Oscillator is presented how much spurious noise effects to RF Receiver system. The main frequency of the proposed Relaxation oscillator is 7.9 MHz to operate it and add temperature compensation block to be applied to the frequency compensation in response to temperature changes. The DC-DC Converter Spurious noise is reduced up to 20 dB through changing frequency randomly. It is fabricated in $0.18{\mu}m$ CMOS technology. The active area occupies an area of $220{\mu}m{\times}280{\mu}m$. The supply voltage is 1.8 V and current consumption is $500{\mu}A$.