• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.110-113
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• 1993

The MOSFET synchronous rectification in the Active-Clamp Forward converter is presented. The Active-Clamp Forward converter has little dead time during the off time of the main switch and it is suitable for the MOSFET synchronous rectification comparing to the other Forward converter topologics. Using the MOSFET synchronous rectification on the Active-Clamp Forward converter with 3.3[V] output and 500[kHz] switching frequency, the improvement of efficiency is achieved comparing with the conventional Schottky barrier diode rectification.

• Journal of international Conference on Electrical Machines and Systems
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• 제2권2호
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• pp.202-215
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• 2013

This paper proposes a SEPIC-input, self-driven, active clamp ZVS converter, where an auxiliary winding and a RC delay circuit are employed to drive the active clamp switch and to achieve asymmetrical duty control without any other extra circuits. Based on the fixed dead time and the resonance between capacitors and inductors, both the main switch and the auxiliary switch can rule the ZVS operation. Detailed operation modes are presented to illustrate the self-driven and ZVS principles. Furthermore, an accurate state-space model and the transfer functions of the proposed converter have been presented and analyzed in order to optimize dynamic performance. The model provides efficient prediction of converter operations. Experimental results, based on a prototype with 80V input and 15V/20A output, are discussed to verify the transient and steady performance of the proposed converter.

• Journal of Power Electronics
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• 제14권3호
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• pp.421-431
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• 2014

A DSP-based self-adaptive proportional-integral (PI) controller to control a DC-DC converter is proposed in this paper. The full-bridge topology is adopted here to obtain higher power output capability and higher conversion efficiency. The converter adopts the zero-voltage-switching (ZVS) technique to reduce the conduction losses. A parallel secondary active clamp circuit is added to deal with the voltage overshoot and ringing effect on the transformer's secondary side. A self-adaptive PI controller is proposed to replace the traditional PI controller. Moreover, the designed converter adopts the constant-current and constant-voltage (CC-CV) output control strategy. The secondary active clamp mechanism is discussed in detail. The effectiveness of the proposed converter was experimentally verified by an IGBT-based 10kW prototype.

• 전력전자학회논문지
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• 제17권3호
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• pp.230-237
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• 2012

This paper proposes an active-clamp ac-dc converter with direct power conversion that has a simple structure and achieves high efficiency. The proposed converter is derived by integrating the step-down ac chopper and the output-voltage doubler. The proposed converter provides direct ac-dc conversion and dc output voltage without using any full-bridge diode rectifier. The step-down ac chopper using an active-clamp mechanism serves to clamp the voltage spike across the main switches and provides zero-voltage turn-on switching. The resonant-current path formed by the leakage inductance of the transformer and the resonant capacitor of the output-voltage doubler achieves the zero-current turn-off switching of the output diodes. The operation principle of the converter is analyzed and verified. A 500W prototype is implemented to show the performance of the proposed converter. The prototype provides maximum efficiency of 95.1% at the full load.

• Journal of Power Electronics
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• 제15권1호
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• pp.86-95
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• 2015

An active clamp high step-up boost converter with a coupled inductor is proposed in this paper. In the proposed strategy, a coupled inductor is adopted to achieve a high voltage gain. The clamp circuit is included to achieve the zero-voltage-switching (ZVS) condition for both the main and clamp switches. A rectifier composed of a capacitor and a diode is added to reduce the voltage stress of the output rectifier diode. As a result, diodes with a low reverse-recovery time and forward voltage-drop can be utilized. Since the voltage stresses of the main and clamp switches are far below the output voltage, low-voltage-rated MOSFETs can be adopted to reduce conduction losses. Moreover, the reverse-recovery losses of the diodes are reduced due to the inherent leakage inductance of the coupled inductor. Therefore, high efficiency can be expected. Firstly, the derivation of the proposed converter is given and the operation analysis is described. Then, a steady-state performance analysis of the proposed converter is analyzed in detail. Finally, a 250 W prototype is built to verify the analysis. The measured maximum efficiency of the prototype is 95%.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 전문대학교육위원 P
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• pp.13-15
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• 1999

The zero voltage and zero current switching(ZVZCS) full bridge (FB) PWM converter using secondary active clamp is characterized by high efficiency, good ZVZCS characteristic, simple topology and low cost. But at the period for discharge of the secondary clamp capacitor, peak pulses and ringing pulse occur in rectified secondary side of the converter. In this paper, a novel secondary active clamp circuit for the ZVZCS FB PWM converter is proposed and a 50 kHz, 500 W prototype converter was experimented for verification of the converter characteristics. It was verified that high voltage peak pulses and ringing pulse on secondary rectified waveforms of the converter are decreased effectively.

• 전력전자학회논문지
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• 제24권4호
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• pp.259-267
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• 2019

An active clamp flyback (ACF) converter applies a clamp circuit and circulates the energy of leakage inductance to the input side, thereby achieving a zero-voltage switching (ZVS) operation and greatly reducing switching losses. The switching losses are further reduced by applying a gallium nitride field effect transistor (GaN-FET) with excellent switching characteristics, and ZVS operation can be accomplished under light load with boundary conduction mode (BCM) operation. Optimal design is performed on the basis of loss analysis by selecting magnetization inductance based on BCM operation and a clamp capacitor for loss reduction. Therefore, the size of the reactive element can be reduced through high-frequency operation, and a high-efficiency and high-power-density converter can be achieved. This study proposes an optimal design for a high-efficiency and high-power-density BCM ACF converter based on GaN-FETs and verifies it through experimental results of a 65 W-rated prototype.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.963_964
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• 2009

This paper presents an output ripple reduction of Active-Clamp Forward Converter, which is mainly composed of interleaving two active-clamping forward converters. By interleaving, Output ripple is reduced. The leakage inductance of the transformer or an additional resonant inductance is employed to achieve ZVS during the dead times. The duty cycles are not limited to be equal and within 50%. The complementary switching and the resulted interleaved output inductor currents diminish the current ripple in output capacitors. Accordingly, the smaller output chokes and capacitors lower the converter volume and increase the power density. Detailed analysis of this ouput reduction of Active-Clamp Forward Converter is described.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.31-32
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• 2015

본 논문은 FAC (Forward converter Active Clamp) 회로를 통해 변압기 자화인덕턴스에 저장된 에너지를 셀 밸런싱에 재사용하는 Active Clamp Forward converter 기반 셀 밸런싱 회로를 제안한다. 제안 회로는 클램프 커패시터의 충전 균형으로 스위치를 전압 스파이크로부터 보호하고 전력손실을 초래할 수 있는 변압기의 자기포화를 방지할 수 있다. 제안한 셀 밸런싱 회로는 RCD 포워드 셀 밸런싱 컨버터 보다 더 높은 전력 전달 효율과 낮은 전압 스트레스를 갖는다. 제안한 액티브 셀 밸런싱 회로는 동시에 모든 셀이 균등화 되도록 작동하므로, 셀밸런싱 시간이 짧다. 본 논문에서는 제안 회로의 배터리 상태에 따른 제어모드를 설명하고 회로의 타당성 검증을 위해 Powersim 사(社)의 Psim 시뮬레이션 연구를 수행하였다.

• 조명전기설비학회논문지
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• 제15권6호
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• pp.49-57
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• 2001

본 논문에서는 single-stage, two-stage 두가지 역률보상(PFC)기법을 기존의 능동 클램프 플라이백 컨버터에 적용하여 역률개선을 하였다. 삽입된 플라이백 컨버터의 능동클램프회로가 주스위치와 보조스위치의 영전압스위칭(ZVS)을 구현하며, 스위칭 손실을 줄임으로써 고효율을 얻을 수 있고, 높은 주파수에서의 스위칭이 가능하다. 하지만 일반적으로 사용되는 다이오드정류기, 평활용커패시터에 의한 낮은 역률의 문제점이 남아있다. 본 논문에서는 300[W급] 능동 클램프 ZVS 플라이백 컨버터를 설계하여 single-stage two-stage방식을 적용, 입력역률개선을 시뮬레이션과 실험에 의해 입증하고자 한다.