• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.44-48
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• 2008

Hole mobility characteristics of two representative biaxially strained SiGe/Si structures with high Ge contents are studied, They are single channel ($Si/Si_{1-x}Ge_x/Si$ substrate) and dual channel ($Si/Si_{1-y}Ge_y/Si_{1-x}Ge_x/Si$ substrate), where the former consists of a relaxed SiGe buffer layer with 60 % Ge content and a tensile-strained Si layer on top, and for the latter, a compressively strained SiGe layer is inserted between two layers, Owing to the hole mobility performance between a relaxed SiGe film and a compressive-strained SiGe film in the single channel and the dual channel, the hole mobility behaviors of two structures with respect to the Si cap layer thickness shows the opposite trend, Hole mobility increases with thicker Si cap layer for single channel structure, whereas it decreases with thicker Si cap layer for dual channel. This hole mobility characteristics could be easily explained by a simple capacitance model.

• 한국정보통신학회논문지
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• 제4권3호
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• pp.713-719
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• 2000

고체상 켜쌓기법(solid phase epitaxy)으로$Ge_xSi_{1-x}/Si$(111) 이종접합을 형성하기 위해 Si(111) 기판위에 먼저 Au를 1000A 증착하고 그 위에 Ge을 1000A 증착시켜 a-Ge/Au/Si(111)구조를 형성하고 이를 고진공 조건에서 이단계 열처리 하였다. 열처리 후 Auger 전자분광분석(AES), X-ray 회절(XRD), 고분해 투과전자현미경(HRTEM) 등을 통해 Au와 Ge의 거동과 형성된 $Ge_xSi_{1-x}$막의 특성을 열처리 조건에 따라 분석하였다. a-Ge/Au/Si(111)구조는 열처리에 의해 Au/GeSi/Si(111)의 구조로 변했으며 형성된$Ge_xSi_{1-x}/$((111)층은 Si(111) 기판의 면 방향과 잘 일치하였다. 그러나 $Ge_xSi_{1-x}/Si$((111)층 내부에 적층결함, 전이, 쌍정, planar defect 등이 주로 (111)면 방향으로 형성되어 있음을 알 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• 한국세라믹학회지
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• 제37권5호
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• pp.432-437
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• 2000

Thermoelectric properties of p-type SiGe alloys prepared by a RF inductive furnace were investigated. Non-doped Si80Ge20 alloys were fabricated by control of the quantity of volatile Ge. The carrier of p-type SiGe alloy was controlled by B-doping. B doped p-type SiGe alloys were synthesized by melting the mixture of Ge and Si containing B. The effects of sintering/annealing conditions and compaction pressure on thermoelectric properties (electrical conductivity and Seebeck coefficient) were investigated. For nondoped SiGe alloys, electrical conductivity increased with increasing temperatures and Seebeck coefficient was measured negative showing a typical n-type semiconductivity. On the other hand, B-doped SiGe alloys exhibited positive Seebeck coefficient and their electrical conductivity decreased with increasing temperatures. Thermoelectric properties were more sensitive to compaction pressure than annealing time. The highest power factor obtained in this work was 8.89${\times}$10-6J/cm$.$K2$.$s for 1 at% B-doped SiGe alloy.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.83.1-83.1
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• 2010

Hydrogenated a-SiGe middle cell for triple junction solar cell was investigated with various process parameters. a-SiGe I-layer was deposited at substrate temperature $245^{\circ}C$ and hydrogen content(R) was up to 26.7. Low optical bandgap(1.45eV) of a-SiGe cell was applied for middle cell although a-SiGe single cell efficiency with low Ge content was higher. And this cell was applied to the middle cell of a glass superstrate type a-Si/a-SiGe/uc-Si triple junction solar cell. The triple junction solar cell was resulted in the initial efficiency of about 9%, area $0.25cm^2$, under global AM 1.5 illumination.

• 한국진공학회지
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• 제20권2호
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• pp.77-85
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• 2011

실리콘(Si)에 비해 상대적으로 밴드 갭이 작고, 열전도도가 낮으며, 기존의 Si 반도체 공정 기술과 호환이 가능한 실리콘-게르마늄(SiGe) 합금은 트랜지스터, 광수신 소자, 태양전지, 열전 소자 등 다양한 전자 소자에서 사용되고 있다. 본 논문에서는 SiGe 합금이 전자소자에 응용되는 원리 및 응용과 관련된 기술적인 논제들을 고찰한다. Si에 비해 밴드 갭이 작은 게르마늄(Ge)이 그 구성 원소인 SiGe 합금의 밴드 갭은 Si과 Ge의 분률과 상관없이 항상 Si의 밴드 갭 보다 작다. 이러한 SiGe의 작은 밴드 갭은 전류 이득의 손실 없이 베이스 두께를 감소시키는 것을 가능하게 하여 바이폴라 트랜지스터의 동작속도를 향상시킨다. 또한, Si이 흡수하지 못하는 장파장 대의 빛을 SiGe이 흡수하여 광전류를 생성하게 함으로써 태양전지의 변환효율을 증가시킨다. 질량이 서로 다른 Si 및 Ge 원소의 불규칙적인 분포에 의해 발생하는 포논 산란 효과 때문에 SiGe 합금은 순수한 Si 및 Ge과 비교할 때 낮은 열전도도를 갖는다. 낮은 열전도도 특성의 SiGe 합금은 전자 소자 구조 내에서의 열 손실을 억제하는데 효과가 있으므로 Si 반도체 공정 기반의 열전 소자의 구성 물질로서 활용이 기대된다.

• 전자공학회논문지D
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• 제36D권4호
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• pp.86-92
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• 1999

SiGe을 이용한 p형 전계 효과 트랜지스터의 전류 구동 능력 향상을 위하여 이중 δ도핑층을 이용한 MESFET을 설계하고 시뮬레이션을 통하여 전기적 특성의 개선을 확인하였다. 두 δ도핑층 사이의 도핑 농도가 낮은 분리층에 SiGe층을 위치시키면 양자 우물이 형성되어 δ도핑층에서 넘쳐 나온 정공이 Si 채널의 경우보다 더 많아져 전류 구동 능력이 크게 향상된다. δ도핑층 사이의 SiGe층의 두께는 0∼300Å, Ge 구성비는 0∼30%의 범위에서 변화시켜 SiGe 두께 200Å, Ge 구성비 30%일 때 이중 δ도핑 Si 채널 MESFET에 비해 최대 45% 이상 개선될 수 있음을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.541-544
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• 1998

A SiGe p-channel MESFET using $\delta-doped$ layers is designed and the considerable enhancement of the current driving capability of the device is observed from the result of simulation. The channel consists of double $\delta-doped$ layers separated by a low-doped spacer which consists of Si and SiGe. A quantum well is formed in the valence band of the Si/SiGe heterojunction and much more holes are accumulated in the SiGe spacer than those in the Si spacer. The saturation current is enhanced by the contribution of the holes inthe spacer. Among the design parameters that affect the performance of the device, the thickness of the SiGe layer and the Ge composition are studied. The thickness of $0~300\AA$ and the Ge composition of 0~30% are investigated, and the saturation current is observed to be increased by 45% compared with a double $\delta-doped$ Si p-channel MESFET.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.