• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 춘계학술대회 및 기술 세미나 논문집 디스플레이 광소자
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• pp.55-56
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• 2008

The photo leakage currents of a conventional hydrogenated amorphous silicon(a-Si:H) thin film transistor(TFT) were investigated and analyzed in the case of illumination from various lightsources such as halogen lamp, cold cathode fluorescent lamp(CCFL) backlight, and white light emitting diode(LED) backlight The photo leakage characteristics showed the apparent differences in the leakage level and in the $I_{on}/I_{off}$ ratio in spite of the similar luminances of light sources. This leakage level is expected to be related to the wavelength of the lowest intensity peak from spectral analysis of light sources.

• E2M - 전기 전자와 첨단 소재
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• 제21권9호
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• pp.25-32
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• 2008

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 춘계학술대회 논문집
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• pp.102-104
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• 1996

The fabrication and analytical expression for the temperature dependent capacitance characteristics of inverted staggered hydrogenerated amorphous silicon thin film transistors(a-si :H TFT) from 303k to 363k were presented. The results show that the experimental capacitance-voltage characteristics at several temperatures are easily measured. Capacitance increased exponentially by gate voltage increase and decreased by temperature increase. C/C(max) ratio decreased at higher temperature, C/C(min) ratio increased at higher temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.173-176
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• 2005

Teijin사의 HT100-B60의 폴리카보네이트(polycarbonate) $100{\mu}m$, I-Component사의 PES(polyethersulfone) $200{\mu}m$, Ferrania사의 PAR(polyacrylate) $100{\mu}m$와 $200{\mu}m$를 사용하였다 열팽창계수의 차이로 인해 공정상 기판의 가열과 냉각시 열응력이 발생하여 기판의 크랙발생의 원인이 된다. 이를 최소화하기 위해 모든 공정이 시작하기 전에 pre-annealing을 통해 plastic 기판의 시간별 공정을 실시하였다. plastic film의 annealing time은 0h, 12h, 24, 40h, 50h, 60h, 70h, 80h으로 사간을 달리하여 오븐 안의 진공상태를 조성하여 실험하였다. Thermal evaporator로 Al을 약 170nm 증착하였으며 (주)동진 세미캠의 DTFR-1011s DR LCD용 감광액을 Spin Coating Spread(500rpm/6sec), Spin(3000rpm/20sec)으로 coating하였다.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.129-129
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• 2003

최근에 능동 영역 액정 표시 소자(Active Matrix Liquid Crystal Display, AMLCD)에서 고해상도와 빠른 응답속도를 요구하게 되면서부터 다결정 실리콘(poly-Si) 박막 트랜지스터(Thin Film Transistor, TFT)가 쓰이게 되었다. 그리고 일반적으로 디스플레이의 기판을 상대적으로 저가의 유리를 사용하기 때문에 저온 공정이 필수적이다. 따라서 새로운 저온 결정화 방법과 부가적으로 최근 디스플레이 개발 동향 중 하나인 대화면에 적용 가능한 공정인 금속유도 결정화 (Silicide Mediated Crystallization, SMC)가 연구되고 있다. 이 소자는 top-gated coplanar구조로 설계되었다. (그림 1)(100) 실리콘 웨이퍼위에 3000$\AA$의 열산화막을 올리고, LPCVD로 55$0^{\circ}C$에서 비정질 실리콘(a-Si:H) 박막을 550$\AA$ 증착 시켰다. 그리고 시편은 SMC 방법으로 결정화 시켜 TEM(Transmission Electron Microscopy)으로 SMC 다결정 실리콘을 분석하였다. 그 위에 TFT의 게이트 산화막을 열산화막 만큼 우수한 TEOS(Tetraethoxysilane)소스로 사용하여 실리콘 산화막을 1000$\AA$ 형성하였고 게이트는 3000$\AA$ 두께로 몰리브덴을 스퍼터링을 통하여 형성하였다. 이 다결정 실리콘은 3$\times$10^15 cm^-2의 보론(B)을 도핑시켰다. 채널, 소스, 드래인을 정의하기 위해 플라즈마 식각이 이루어 졌으며, 실리콘 산화막과 실리콘 질화막으로 passivation하고, 알루미늄으로 전극을 형성하였다 그리고 마지막에 TFT의 출력특성과 전이특성을 측정함으로써 threshold voltage, the subthreshold slope 와 the field effect mobility를 계산하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.257-260
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• 2007

Hydrogenated amorphous silicon thin film transistors were fabricated on a flexible metal substrate. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and gate electrode. This can recover the shifted-threshold voltage to an original value.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

• 대한전기학회논문지
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• 제41권2호
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• pp.163-169
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• 1992

A new analytical expression for the temperature variation characteristics of hydrogenerated amorphous silicon thin film transistors(a-si:H TFT), between 223K and 433K, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled between -5$0^{\circ}C$ and 9$0^{\circ}C$. The model is based on three functions obtained from the experimental data of IS1DT versus VS1GT. Theoretical results confirm the simple form of the model in terms of the device geometry. It was determined that as the temperature increased, the saturated drain current increased and, at a fixed gate voltage, the device saturated at increasingly larger drain voltages while the threshold voltages decreased.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1697-1700
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• 2006

A Novel pixel structure with a new threshold voltage compensation technique is proposed for large-size a-Si:H AMOLED panel application. The proposed pixel improves image quality with threshold voltage compensation and alleviates annealing technique for display-off time. Sensing the threshold voltage of driving TFT for 20-inch WUXGA panel is verified by the HSPICE simulation.