• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.577-578
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• 2008

This paper proposes new analog ZQ calibration scheme. Proposed analog ZQ calibration scheme is for minimizing the reflection which degrade the signal integrity. And this scheme is for minimizing CIO capacitance. It is simulated under 1.5v supply voltage and samsung 0.18um process. Power consumption of proposed analog ZQ calibration circuit was improved by 32%. Under all skew, temperature from $30^{\circ}C$ to $90^{\circ}C$ and Monte carlo simulation, quantization error of RZQ(=$240{\Omega}$) is less han 1.07%.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.579-580
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• 2008

DRAM설계시 DDR2에서부터 고속 동작으로 인해 반송파에 의한 신호외곡으로 impedance matching의 필요성이 대두되었다. 이로 인해 제안된 방법은 외부 Termination 저항(RZQ)을 기준으로 impedance matching을 위한 Rtt 저항의 생성이다.[1] 제안된 ZQ Calibration 회로는 기존의conventional ZQ Calibration 회로에 After ZQ calibration block을 추가하여 한 번 더 교정함으로써 마지막 PMOS Array와 NMOS Array 저항 값이 Termination 저항 값에 가깝도록 설계하였다. 따라 전력효율은 그대로 유지하면서 ${\Delta}VM$의 오차범위를 기존의 ${\pm}5%$이내에서 skew 조건에 따라 ${\pm}1.33%$까지 향상시키는 것을 볼 수 있다. (JEDEC spec. ${\pm}5%$이내).

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.417-422
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• 2021

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.