• Title/Summary/Keyword: Y-capacitors

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Fabrication of Niobium Powder for Solid-electrolyte Capacitors (고체 전해커패시터용 니오븀 분말제조)

  • Yoon, Jae-Sik;Hwang, Sun-Ho;Kim, Byung-Il
    • Journal of the Korean institute of surface engineering
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    • v.42 no.5
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    • pp.227-231
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    • 2009
  • The niobium capacitor showed somewhat more unstable characteristics than the commercial tantalum capacitors, but is nonetheless considered applicable as a future substitute for tantalum capacitors. In this study, niobium powder was fabricated by metallothermic reduction process using $K_2NbF_7$ as the raw materials, KCl and KF as the diluents and Na as the reducing agent. The niobium particle size greatly decreased from 0.7um to 0.2 um as the amount of diluent increased. However if a higher surface area of powder is required, more diluents need to be used in the said method in order to produce niobium powder. The niobium powder morphology and particle size are very sensitive to a amount of sodium excess. The particle size of niobium powder increased with a increasing amount of sodium excess. When more diluent and sodium are used, the niobium powder will be contaminated with more impurities such as Fe, Cr, Ni so on.

Electrical charateristics of MIS BST thin films

  • Park, C.-S.;Mah, J.-P.
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.14 no.3
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    • pp.90-94
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    • 2004
  • The variation of electrical properties of (Ba,Sr)$TiO_3$ [BST] thin films for Metal-Insulator-Semiconductor (MIS) capacitors was investigated. BST thin films were deposited on p-Si(100) substrates by the RF magnetron sputtering with temperature range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of AUBST/$SiO_2$/Si sandwich structure were measured for various conditions. We examined the characteristics of MIS capacitor with various oxygen pressure, substrate temperature and (Ba+Sr)/Ti ratio. It was found that the leakage current was reduced in MIS capacitor with high quality $SiO_2$ layer was grown on bare p-Si substrate by thermal oxidation. The BST MIS structure showed relatively high capacitance even though it is the combination of high-dielectric BST thin films and $SiO_2$ layer. The charge state densities of the MIS capacitors and Current-voltage characteristics of the MIS capacitor were investigated. By applying $SiO_2$ layer between BST thin films and Si substrate, low leakage current of $10^{-10}$ order was observed.

Ferroelectrical Properties of SBT Capacitors with various Annealing Atmosphere (다양한 열처리 분위기에 따른 SBT 커패시터의 강유전체 특성)

  • Cho, Choon-Nam;Oh, Young-Choul;Kim, Jin-Sa;Choi, Woon-Shik;Kim, Chung-Hyeok;Park, Young-Pil;Hong, Jin-Woong;Lee, Joon-Ung
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.05d
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    • pp.72-76
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    • 2003
  • The $Sr_{0.7}Bi_{2.6}Ta_2O_9$(SBT) thin films are deposited on Pt-coated electrode(Pt/$TiO_2/SiO_2$/Si) using RF magnetron sputtering method. The structural and electrical properties of SBT capacitors were influenced with annealing atmosphere. In the XRD pattern, the SBT thin films in all annealed atmosphere had (105) orientation. In the SEM images, Bi-layered perovskite phase was crystallized in all annealing atmosphere and grains largely grew in oxygen annealing atmosphere. The maximum remanent polarization and the coercive electric field in oxygen annealing atmosphere are $12.40[{\mu}C/cm^2]$ and 30[kV/cm] respectively. The fatigue characteristics of SBT capacitors did not change up to $10^{10}$ switching cycles.

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Reliability Evaluation and failure Analysis for High Voltage Ceramic Capacitor (고압 커패시터의 고장분석과 신뢰성 평가)

  • 김진우;송옥병;신승우;이희진;신승훈;유동수
    • Proceedings of the Korean Reliability Society Conference
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    • 2001.06a
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    • pp.337-337
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    • 2001
  • High voltage ceramic capacitors are widely applied in power electronic circuits, such as filters, snubbers, and resonant circuits, due to their excellent features of high voltage endurance and low aging. This paper presents a result of failure analysis and reliability evaluation for high voltage ceramic capacitors. The failure nodes and failure mechanisms were identified in order to understand the failure physics in a component. The causes of failure mechanisms for zero resistance phenomena under withstanding voltage test in high voltage ceramic capacitors molded by epoxy resin were studied by establishing an effective closed-loop failure analysis. Also, the condition for dielectric breakdown was investigated. Particular emphasis was placed on breakdown phenomena at the ceramic-epoxy interface. The validity of the results in this study was confirmed by the results of accelerated testing. Thermal shock test as well as pressure cooker test for high voltage ceramic capacitor mounted on a magnetron were implemented. Delamination between ceramic and epoxy, which, might cause electrical short in underlying circuitry, can occur during curing or thermal cycling. The results can be conveniently used to quickly identify defective lots, determine mean time to failure (MTTF) of each lot at the level of Inspection, and detect major changes in the vendors processes.

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High Security FeRAM-Based EPC C1G2 UHF (860 MHz-960 MHz) Passive RFID Tag Chip

  • Kang, Hee-Bok;Hong, Suk-Kyoung;Song, Yong-Wook;Sung, Man-Young;Choi, Bok-Gil;Chung, Jin-Yong;Lee, Jong-Wook
    • ETRI Journal
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    • v.30 no.6
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    • pp.826-832
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    • 2008
  • The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

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Reference Model Updating of Considering Disturbance Characteristics for Fault Diagnosis of Large-scale DC Bus Capacitors (대용량 직류버스 커패시터의 고장진단을 위한 외란특성 반영의 레퍼런스 모델 개선)

  • Lee, Tae-Bong
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.66 no.4
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    • pp.213-218
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    • 2017
  • The DC electrolytic capacitor for DC-link of power converter is widely used in various power electronic circuits and system application. Its functions include, DC Bus voltage stabilization, conduction of ripple current due to switching events, voltage smoothing, etc. Unfortunately, DC electrolytic capacitors are some of the weakest components in power electronics converters. Many papers have proposed different algorithms or diagnosis method to determinate the ESR and tan ${\delta}$ capacitance C for fault alarm system of the electrolytic capacitor. However, both ESR vary with frequency and temperature. Accurate knowledge of both parameters at the capacitors operating conditions is essential to achieve the best reference data of fault alarm. According to parameter analysis, the capacitance increases with temperature and the initial ESR decreases. Higher frequencies make the reference ESR with the initial ESRo value to decrease. Analysis results show that the proposed DC Bus electrolytic capacitor reference ESR model setting technique can be applied to advanced reference signal of capacitor diagnosis systems successfully.

Impact of Fixed Series Capacitors and SSSC on the LOE Protection of Synchronous Generator

  • Ghorbani, Amir;Lima, Hossein Mehryari;Azadru, Allahverdi;Mozafari, Babak
    • Journal of Electrical Engineering and Technology
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    • v.10 no.4
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    • pp.1453-1459
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    • 2015
  • Loss of excitation (LOE) relay is prevalently used to protect synchronous generator. The widely used method for synchronous generator LOE protection is a negative offset mho relay with two zones. The basis of this relay is identical to mho impedance relay. In other words, this relay calculates impedance by measuring voltage and current at the generator terminal. On the other hand, the presence of series compensation, changes measured voltage and current signals during loss of excitation. This paper reveals that the presence of series compensators such as fixed series capacitors (FSCs) and static synchronous series compensator (SSSC) causes a significant delay on the performance of generator LOE relay. It is also shown that the presence of SSSC causes the LOE relay to be under-reached. Different operating modes of the power system, the SSSC and also different percentages of series capacitive compensations have been considered in the modeling. All the detailed simulations are carried out in the MATLAB/Simulink environment using the SimPowerSystems toolbox.

Effects of Sputtering Pressure on the Properties of BaTiO3 Films for High Energy Density Capacitors

  • Park, Sangshik
    • Korean Journal of Materials Research
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    • v.24 no.4
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    • pp.207-213
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    • 2014
  • Flexible $BaTiO_3$ films as dielectric materials for high energy density capacitors were deposited on polyethylene terephthalate (PET) substrates by r.f. magnetron sputtering. The growth behavior, microstructure and electrical properties of the flexible $BaTiO_3$ films were dependent on the sputtering pressure during sputtering. The RMS roughness and crystallite size of the $BaTiO_3$ increased with increasing sputtering pressure. All $BaTiO_3$ films had an amorphous structure, regardless of the sputtering pressures, due to the low PET substrate temperature. The composition of films showed an atomic ratio (Ba:Ti:O) of 0.9:1.1:3. The electrical properties of the $BaTiO_3$ films were affected by the microstructure and roughness. The $BaTiO_3$ films prepared at 100 mTorr exhibited a dielectric constant of ~80 at 1 kHz and a leakage current of $10^{-8}A$ at 400 kV/cm. Also, films showed polarization of $8{\mu}C/cm^2$ at 100 kV/cm and remnant polarization ($P_r$) of $2{\mu}C/cm^2$. This suggests that sputter deposited flexible $BaTiO_3$ films are a promising dielectric that can be used in high energy density capacitors owing to their high dielectric constant, low leakage current and stable preparation by sputtering.

Fabrication of Mesoporous Carbon Nanofibers for Electrical Double-Layer Capacitors (전기 이중층 커패시터용 메조 다공성 탄소 나노섬유의 제조)

  • Lee, Do-Young;An, Geon-Hyoung;Ahn, Hyo-Jin
    • Korean Journal of Materials Research
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    • v.27 no.11
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    • pp.617-623
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    • 2017
  • Mesoporous carbon nanofibers as electrode material for electrical double-layer capacitors(EDLCs) are fabricated using the electrospinning method and carbonization. Their morphologies, structures, chemical bonding states, porous structure, and electrochemical performance are investigated. The optimized mesoporous carbon nanofiber has a high sepecific surface area of $667m^2\;g^{-1}$, high average pore size of 6.3 nm, and high mesopore volume fraction of 80 %, as well as a unifom network structure consiting of a 1-D nanofiber stucture. The optimized mesoporous carbon nanofiber shows outstanding electrochemical performance with high specific capacitance of $87F\;g^{-1}$ at a current density of $0.1A\;g^{-1}$, high-rate performance ($72F\;g^{-1}$ at a current density of $20.0A\;g^{-1}$), and good cycling stability ($92F\;g^{-1}$ after 100 cycles). The improvement of the electrochemical performance via the combined effects of high specific surface area are due to the high mesopore volume fraction of the carbon nanofibers.

Passive Power Factor Correction Circuits for Electronic Ballasts using Voltage-Fed and Current-Fed Resonant Inverters (전압원 및 전류원 구동 공진형 인버터로 구성된 형광등용 전자식 안정기의 역률개선에 적합한 수동 역률 개선 회로에 관한 연구)

  • Chae, Gyun;Ryu, Tae-Ha;Cho, Gyu-Hyung
    • Proceedings of the KIPE Conference
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    • 1999.07a
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    • pp.266-269
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    • 1999
  • Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

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