• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.56-62
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• 1999

All the cells on the whole memory array or a block of the memory array in the Flash EEPROM's are erased at the same time using Fowler-Nordheim (FN) tunneling. some of the cels are often overerased since the tunneling is not a self-limited process. In this paper, the optimum doping concentration of the floating gate solve the overerase problem has been studied. For these studies, N-type MOSFETs and MOS capacitors with various doping concentrations of the gate polysilicon have been fabricated and their electrical characteristics have been measured and analyzed. As the results of the experiment, it has been found that the overerase problem can be prevented if the doping concentration of the floating gate is low enough (i.e. below $1.3{\times}10^{18}/cm^3$). It is because the potential difference between the floating gate and the source is lowered due to the formation of the depletion layer in the floating gate and thus the erasing operation stops by itself after most of the electrons stored in the floating gate are extracted. On the other hand, the uniformity of the Vt and the gm has been significantly poor if the coping concentration of the floating, gate is too much lowered (i.e. below $1.3{\times}10^{17}/cm^3$), which is believed to be due to nonuniform loss of the dopants from the nonuniform segregation in the floating gate. Consequently, the optimum doping concentration of the floating gate to suppress the overerase problem and get the uniform Vt and has been found to range from $1.3{\times}10^{17}/cm^3$ to $1.3{\times}10^{18}/cm^3$ in the Flash EEPROM.

• Journal of the Korean Electrochemical Society
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• v.5 no.3
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• pp.117-124
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• 2002

Poly(acrylonitrile)(PAN) solutions in dimethylformamide(DMF) were electrospun to prepare webs consisting of 400nm ultra-fine fibers. The webs were oxidatively stabilized, activated by steam and resulted to be activated carbon fibers(ACFs). The specific surface area was $800\~1230 m^2/g$, which showed a trend of a decrease of the surface area with an increase in activation temperature, showing opposite behavior to the other ACFs. The activation energy of the stabilized fibers for the steam activation was determined as 29.2 kJ/mol to be relatively low indicating the easier activation than that of other carbonized fibers. The ACF webs were characterized by pore size and specific surface uea which would be related to the specific capacitance of the electrical double layer capacitor (EDLC). The specific capacitances measured were 27 F/g, 25 F/g, 22 F/g at the respective activation temperature of $700^{circ}C,\;750^{\circ}C\;800^{\circ}C$, showing similar trend with the specific surface area i.e., the higher activation temperature was, the lower specific capacitance resulted.

• Composites Research
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• v.32 no.6
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• pp.301-306
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• 2019

Triboelectric nanogenerator (TENG) is one of the energy harvesting methods in spotlight that can convert mechanical energy into electricity. As TENGs produce high electrical output, previous studies have shown TENGs that can power small electronics independently. However, recent studies have reported limitations of TENG due to air breakdown and field emission. In this study, we developed a triboelectric nanogenerator that utilizes the metal-to-metal surface contact to induce ion-enhanced field emission and electron avalanche for electrons to flow directly between two electrodes. The average peak open-circuit voltage of this TENG was measured as 340 V, and average peak closed-circuit current was measured as 10 mA. The electrical output of this TENG has shown different value depending on the surface charge of surface charge generation layer. The TENG developed in this study have produced RMS power of 0.9 mW, which is 2.4 times higher compared to conventional TENGs. The TENG developed in this study can be utilized in charging batteries and capacitors to power portable electronics and sensors independently.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.7-12
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• 2003

The $Bi_{3.3}La_{0.7}O_{12}$(BLT) capacitors with Metal-Ferroelectric-Insulator-Silicon structure were prepared on $SiO_2/Si$ substrates by using sol-gel method. The BLT thin films annealed at $650^{\circ}C$ and $700^{\circ}C$ showed randomly oriented perovskite crystalline structures. The full with at half maximum (FWHM) of the (117) main peak was decreased from $0.65^{\circ}$ to $0.53^{\circ}$ with increasing the annealing temperature from $650^{\circ}C$ to $700^{\circ}C$, indicating the improvement in the crystalline quality of the film. In addition, the grain size and $R_rms$ , values were increased with increasing the annealing temperatures, showing the rough film surface at higher annealing temperatures. From the capacitance-voltage (C-V) measurements, the memory window voltage of the BLT film annealed at $700^{\circ}C$ was found to be about 0.7 V at an applied voltage of 5 V. The leakage current density of the BLT film annealed at $700^{\circ}C$ was about $3.1{\times}10^{-8}A/cm^2$.

• Journal of the Korean Ceramic Society
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• v.42 no.2 s.273
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• pp.81-87
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• 2005

The compositions for LTCC embedded capacitors based on $BaTiO_3$ ceramics with $5\~15\;wt\%$ of lithium-borosilicate glass frits were studied. After the glass frits, which is chemically stable and has acceptable ability of low-temperature sintering, were added to the host dielectric materials, the sintering behavior and dielectric properties were evaluated. As for $BaTiO_3$, relative density of >$95\%$, permittivity 990, and dielectric loss $3.1\%$ were obtained when sintered at $925^{\circ}C$ with 5 wt$\%$ of glass frits. As for $(Ba,Ca)(Ti,Zr)O_3$ ceramics, relative density of >$95\%$, open porosity <$0.5\%$, permittivity 700, and dielectric loss $2\%$ were obtained when sintered at $875^{\circ}C$ with 10 wt$\%$ of glass frits.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.123-130
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• 2016

High-frequency induction heating equipment can heat the metal by applying a High-Frequency power to the resonant circuit. The resonance circuit is composed of the work coil and the conduction-cooled power capacitor, it influences the performance of the heat treatment equipment according to the characteristics of the capacitor. However, dependence on conduction-cooled power capacitor's import is high due to lack of core technology research and development. Minimizing the generation of internal heat transmitted inside during LC resonance, reduce the reactive power loss, there is a need for a capacitor within the voltage characteristic outstanding. To implement localization it is vital that prior study of the analysis on the frequency response characteristic for the finished capacitor advanced manufacturer be implemented. Studying the interpolation method to read the value at any point of the characteristic curve for a given log-log scale was applied to the analysis tool of the capacitor by my proposed algorithm. The simulation for reproducing frequency response curves was attempted by assuming a capacitor in a simplified series equivalent RC circuit to obtain the equivalent series resistance value. It was confirmed that the reproduction rate was the result value above 83% as compared to the simulation of the properties and characteristics on the actual reactive power for Peak value, and that the algorithm can be applicable when analyzing and predicting the characteristic curves of a simpled model capacitor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.7
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• pp.683-693
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• 2011

In this paper, a design of high current and broad-band microwave bias-tee was presented for a stable bias of a high power amplifier. An input impedance of bias-tee should be shown to 50 ohm with the wideband in order to be stably-biased the amplifier. For this design of the bias-tee, a capacitor of bias-tee for a DC block was designed with a high wide-band admittance by a parallel sum of capacitors, and a inductor for a RF choke and a DC feeding was designed with a high wide-band impedance by a series sum of inductors. As this inductor and capacitor for the sum has each SRF, band-limitation of lumped element was driven from SRF. This limitation was overcome by control of a resonance's quality factor with adding a resistor. 1608 SMD chips for design's element was mounted on the this pattern for the designed bias-tee. The fabricated bias-tee presented 10 dB of return loss and wide-band about 50 ohm input impedance at 10 MHz~10 GHz.

• The Journal of the Acoustical Society of Korea
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• v.20 no.5
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• pp.69-75
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• 2001

In this paper, a fast and easy impedance matching method, which could give the impedance matching component for the general 1 or 2-port network was introduced. First, the entire network structure was defined which consists of the network part to be matched and the impedance matching part composed of inductors and capacitors. Next, the transmission matrix and input and output impedances of the entire network from the terminal impedance conditions were calculated, then the exact solutions for the matching components were obtained. To verify the efficiency of this method, this method was applied to the CDMA If band withdrawal weighted SAW transversal filter, and investigated the effects of the impedance matching before and after, through the simulation and experiment. As the result, the performance of a fractional bandwidth of 1.2%, insertion loss of 29 dB, and VSWR of 80 have improved to a factional bandwidth of 1.8％, insertion loss of 9 dB, VSWR of 3 at 85.38 MHz center frequency. The result shows that this impedance matching method could be used in the SAW devices and other types of 1 or 2-port network.