• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.2
• /
• pp.439-446
• /
• 2019

In this paper, we propose a encryption method using C-MLCA and 1D CAT to secure medical image for efficiently. First, we generate a state transition matrix using a Wolfram rule and create a sequence of maximum length. By operating the complemented vector, it converts an existing sequence to a more complex sequence. Then, we multiply the two sequences by rows and columns to generate C-MLCA basis images of the original image size and go through a XOR operation. Finally, we will get the encrypted image to operate the 1D CAT basis function created by setting the gateway values and the image which is calculated by transform coefficients. By comparing the encrypted image with the original image, we evaluate to analyze the histogram and PSNR. Also, by analyzing NPCR and key space, we confirmed that the proposed encryption method has a high level of stability and security.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.43 no.5 s.311
• /
• pp.36-43
• /
• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.18 no.2
• /
• pp.3-10
• /
• 2008

The choice of basis for representation of element in $GF(2^m)$ affects the efficiency of a multiplier. Among them, a multiplier using redundant representation efficiently supports trade-off between the area complexity and the time complexity since it can quickly carry out modular reduction. So time of a previous multiplier using redundant representation is faster than time of multiplier using others basis. But, the weakness of one has a upper space complexity compared to multiplier using others basis. In this paper, we propose a new efficient multiplier with consideration that polynomial exponentiation operations are frequently used in cryptographic hardwares. The proposed multiplier is suitable fer left-to-right exponentiation environment and provides efficiency between time and area complexity. And so, it has both time delay of $T_A+({\lceil}{\log}_2m{\rceil})T_x$ and area complexity of (2m-1)(m+s). As a result, the proposed multiplier reduces $2(ms+s^2)$ compared to the previous multiplier using equally-spaced polynomials in area complexity. In addition, it reduces $T_A+({\lceil}{\log}_2m+s{\rceil})T_x$ to $T_A+({\lceil}{\log}_2m{\rceil})T_x$ in the time complexity.($T_A$:Time delay of one AND gate, $T_x$:Time delay of one XOR gate, m:Degree of equally spaced irreducible polynomial, s:spacing factor)

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.3
• /
• pp.707-714
• /
• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.10a
• /
• pp.343-346
• /
• 2009

Since an LFSR as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for a pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers have studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.5
• /
• pp.55-65
• /
• 2000

In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

• The Journal of Engineering Research
• /
• v.2 no.1
• /
• pp.31-37
• /
• 1997

This paper describes the design and implementation of 8 bit ALU graphic simulator which helps students who study the structure and operation course of general ALU. ALU of this paper consists of three parts, arithmetic circuit, logic circuit, and shifter. Each of them performs as follows. Arithmetic circuit performs arithmetic operation such as addition, subtraction, 1 increment, 1 decrement, 2's complement, logic circuit performs logic operation such as OR, AND, XOR, NOT, and shifter performs shift operation and transfers the result of circuits of arithmetic, logic to data bus. The instructions which relate to these basic ALU functions was selected from Z80 instructions and ALU circuit was designed with those instructions and this designed ALU circuit was implemented on graphic screen. And all state of this data operation course in ALU was showed by bit and logic gate unit.