• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• KIPS Transactions on Computer and Communication Systems
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• v.12 no.1
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• pp.1-8
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• 2023

It is impossible to overwrite on an already allocated page in SSDs, so whenever a write operation occurs a page replacement with a clean page is required. To resolve this problem, SSDs have an internal flash translation layer called FTL that maps logical pages managed by a file system of operating system to currently allocated physical pages. SSD pages discarded due to write operations must be recycled through initialization, but since the number of initialization times is limited the FTL provides a caching function to reduce the number of writes in addition to the page mapping function, which is a core function. In this study, we focus on the FTL cache methodologies reducing the number of page writes and analyze the related algorithms, and propose a write-only cache strategy. As a result of experimenting with the write-only cache using a simulator, it showed an improvement of up to 29%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.129-134
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• 2015

This paper analyzes file access characteristics of smartphone apps and finds that a large portion of file writes are performed only once. Based on this observation, we present a new buffer cache management scheme that considers this characteristics. Buffer cache improves storage performance by maintaining hot file data in memory thereby servicing subsequent requests without storage accesses. However, it should flush modified data to storage in order to resist system crashes. The proposed scheme evicts cache data that has been written only once upon flushes, thus improving cache space utilization. Simulation experiments show that the proposed scheme improves cache hit ratio by 5-33% and power consumption by 27-92%.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.71-78
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• 2019

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.23-31
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• 2011

Recently, Solid state disk is mainly used because this device has lower power consumption as well as higher response time. But it features higher price and lower performance at delete and write operations compared with HDD. To compensate this defect, Hybrid hard disk with internal non-volatile flash memory was issued. This NVCache is used as a kind of cache for disk blocks. In this paper, an I/O scheme for H-HDD is proposed for improving low power consumption as well as response time. Our method is to use this NVCache as read cache mainly and write cache when write requests are concentrated. In read cache operation, disk blocks with higher priority determined on basis of time as well as spatial localities are prefetched, which can improve response time. The write operation is conducted only at write peak time as disk spindle up costs higher battery power as well as response time. Experiments results show that the suggested method can improve response time of H-HDD and lower the power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.546-553
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• 2015

Recently, flash cache is widely adopted as the performance accelerator of legacy storage systems. Unlike other cache media, flash cache should be carefully managed as it has peculiar characteristics such as long write latency and limited P/E cycles. In particular, we make two prominent observations that can be utilized in managing flash cache. First, a serious worn-out problem happens when the working-set of a system is beyond the capacity of flash cache due to excessively frequent cache replacement. Second, more than 50% of data has no hit in flash cache as it is a second level cache. Based on these observations, we propose a cache admission control policy that does not cache data when it is first accessed, and inserts it into the cache only after its second access occurs within a certain time window. This allows the filtering of data disruptive to flash cache in terms of endurance and performance. With this policy, we prolong the lifetime of flash cache 2.3 times without any performance degradations.

• The Transactions of the Korea Information Processing Society
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• v.7 no.12
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• pp.3964-3975
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• 2000

There are two policies for maintaining consistency among the multiple processor caches in a multiprocessor system: Write invalidate and Write update. In the write invalidate policy, whenever a processor attempt to write its cached block, it has to invalidate all the same copies of the updated block in the system. As a results of this frequent invalidations, this policy results in high cache miss ratio. On the other hand, the write update policy renew them, instead of invalidating all the same copies. This policy has to transfer the updated contents through interconnection network, whether the updated block is ptivate or not. Therefore the network suffer from heavy transaction traffic. In this paper we present an efficient cache coherence protocol for shared memory multiprocessor system connected by slotted ring. This protocol is based on the write update policy, but the updated contents are transferred only in case of updating the shared block. Otherwise, if the updated block is private, the updated contents are not transferred. We analyze the proposed protocol and enforce simulation to compare it with previous version.

• Journal of KIISE
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• v.42 no.8
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• pp.954-960
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• 2015

It is important to improve the performance of storage in the home cloud environment within the virtualized IoT gateway since the performance of applications deeply depends on storage. Though SSD caching is applied in order to improve the storage, it is only used for read-cache due to the limitations of SSD such as poor write performance and small write endurance. However, it is important to improve performance of the write operation in the home cloud server, in order to improve the end-user experience. This paper propose a novel SSD caching which considers write-data as well as read-data. We validate the enhancement in the performance of random-write by transforming it to the sequential patterns.

• Journal of KIISE
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• v.41 no.11
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• pp.878-884
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• 2014

File I/O buffer cache plays an important role in narrowing the wide speed gap between the main memory and the secondary storage. However, data loss or inconsistencies may occur if the system crashes before the data that has been updated in the buffer cache is flushed to storage. Thus, most operating systems adopt a daemon that periodically flushes dirty data to the secondary storage. In this study, we show that periodic flushes account for 30-70% of the total write traffic to storage and remove this inefficiency by implementing a small, non-volatile buffer cache. Specifically, we present space-efficient management techniques, such as delta-write and fragment-grouping, and show that the storage write traffic and throughput can be improved by a margin of 44.2% and 23.6%, respectively, with only a small NVRAM.

• The Journal of the Korea Contents Association
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• v.7 no.8
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• pp.21-30
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• 2007

Due to the growth of embedded systems and the development of semi-conductor and storage devices, digital convergence devises is ever growing. Digital convergence devices are equipments into which various functions such as communication, playing movies and wave files and electronic dictionarys are integrated. Example are portable multimedia players(PMPs), personal digital assistants(PDAs), and smart phones. Therefore, these devices need an efficient file system which manages and controls various types of files. In designing such file systems, the size constraint for small embedded systems as well as performance and compatibility should be taken into account. In this paper, we suggest the partial buffer cache technique. Contrary to the traditional buffer cache, the partial buffer cache is used for only the FAT meta data and write-only data. Simulation results show that we could enhance the write performance more than 30% when the file size is larger than about 100 KBytes.