• Textile Coloration and Finishing
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• v.19 no.2
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• pp.24-31
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• 2007

This paper addresses factors of line image quality on grain leather printed via inkjet printer. Lines were printed onto coated leather media, and line width, edge blurriness, and edge raggedness were evaluated for line image quality. Various factors influenced to wetting and capillary wicking were studied and found out that wicking through capillary between fibers causes significant feathering on leather surface similar with pulp capillary in copy Paper. Polyurethane and acrylic resin coating resulted good image qualify by reducing capillary wicking. The mixture of polyurethane and acrylic resin applied on grain leather satisfied with both image quality and surface hand. $AllWrite^{TM}$ ink brought best results of image quality, comparing with $VeraPrint^{TM}$ ink and $JetWrite^{TM}$ ink.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.266-268
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• 2015

In this paper, we write about EDISON program. We study about where to use this program. We can use this program for FEA naturally. But we study that using this program in class. Many students can't understand many mechanics of materials' problem. They want to see image such as change of beam. It can help students to understand many problem. We can use ANSYS or Abaqus. But EDISON program is better for students because of it is freeware. In this paper, I write two problem. One is peak stress of basic beam, another is shearing stress flow of I-beam. On the basis of this, EDISON program will be widely used.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.23-25
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• 1996

In this paper aims at studying the minimal test pattem of the RAM. This also propose a scheme of testing faults from the new fault model using the LLB. The length of test patterns are 6N(1-wsf), 9.5N(2-wsf), 7N(3-wsfl, 3N(4-wsf) operations in N-bit RAM. This test techniques can write into memory cell the number of write operations is reduced and then much testing time is saved. A test set which detects all positive-negative static t-ws faults for t=0, 1, 2, 3, 4 and detects all pattern sensitive fault in memory array. A new fault model, which encompasses the existing fault model Is proposed.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2003.05a
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• pp.3-7
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• 2003

For high performance Grid environments, an efficient GIS(Grid Information Service is required In the Metacomputing Directory Service(MDS) of the Glogus middleware, the Lightweight Directory Access Protocol(LDAP), which is a distributed directory service protocol, is used. The LDAP GIS differs from general purpose LDAP directories in that most of the LDAP operations are write in Grid environments. To get an efficient design of the GIS, it is thus required to analyze the performance of the LDAP system in the context of Grid environments. This paper presents the result of a performance analysis of LDAP systems. The main objective of the evaluation is to see the performance scalability of the LDAP system in the Grid environment where the write operations prevails. Based on these results, we suggest directions of an efficient LDAP-based GIS for a high performance Grid.

• International journal of advanced smart convergence
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• v.5 no.4
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• pp.40-47
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• 2016

Journalism robot by using a computer algorithm, while maintaining the precision and reliability of the existing media refers to an article which is automatically created. In this paper, we introduce 'stock robot' of robot journalism which writes securities articles and describe artificial intelligence algorithms in stages. Key steps of stock robot implemented artificial intelligence algorithm through four steps of data collection and storage, key event extraction, article content production, and article production. This research has developed a stock robot that collects and analyzes data on social issues and stock indexes for the last 2 years. In the future, as the algorithm is further developed, it becomes possible to write securities articles quickly and accurately through social issues. It will also provide customized information tailored to the user's preferences.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.561-562
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• 2006

This paper presents an SRAM which uses the technique to equalize the internal cell node by adding an NMOS transistor. Accordingly, the write driver operates rapidly in a differential current of bit lines, and the operation speed of SRAM improves. An SRAM was implemented with a memory cell, a sense amplifier and a write driver. The SRAM obtained the performance of 18% power reduction and improvement of 56% operation speed. And Power delay product was reduced with 63%. The proposed SRAM was designed based on a 0.35um 1P4M CMOS technology.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.118-129
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• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

• Proceedings of the Korean Society of Computer Information Conference
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• 2012.07a
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• pp.297-300
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• 2012

현재 cache의 성능 향상을 위한 많은 기법들이 제안되고 있으며, Latency Hiding 기법 역시 cache의 효율적인 사용을 위해 많은 연구가 진행 되어 왔다. write buffer를 사용한 write Latency hiding기법이나 multi threading을 사용한 Latency Hiding 방법 등 여러 기법들이 연구되어 왔으며, 지금도 Latency hiding을 위한 많은 연구들이 지속적으로 진행되고 있다. 본 논문 역시 효율적인 Latency Hiding을 위한 누적 버퍼를 제안한다. 본 논문은 누적 버퍼의 활용도를 조사하여 얼마나 효율적으로 Latency를 은폐했는지, 또 버퍼를 사용함으로써 얻는 다른 이점에 대해 집중적으로 연구하였다.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1347-1348
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• 2006

기존 반도체공정들이 갖는 리소그래피와 식각 등의 공정단계를 배제하는 direct-write 공정을 이용하여 친환경적인 이점을 가질 수 있는 나선형 인덕터의 구조를 제안하고 주파수 특성을 확인하였다. 인덕터의 구조는 Si를 $300{\mu}m$, $SiO_2$를 $3{\mu}m$으로 하였으며, CU 코일의 폭과 선간의 간격은 LAM 공정과 direct-write 공정을 이용할 수 있도록 각각 $100{\mu}m$으로 설정하여 3회 권선하였다. 인덕터는 200-500MHz 범위에서 3.5nH의 인덕턴스, 4GHz에서 최대 29 정도의 품질계수를 가지며, SRF는 2.6GHz로 시뮬레이션 결과를 얻을 수 있었다.