• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2006.05a
• /
• pp.21-22
• /
• 2006

Abstract should be written in English using Times New Roman 9pt. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2006.05a
• /
• pp.545-546
• /
• 2006

Abstract should be written in English using Times New Roman 9pt. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here. Write English abstract here.

• Proceedings of the KIEE Conference
• /
• 2001.07b
• /
• pp.626-628
• /
• 2001

고 기록 밀도의 HDD를 위해서는 HDD Media의 선 기록 밀도와 트랙 밀도를 높여야 한다. 선기록 밀도를 높이기 위해서는 HDD Write Head의 Field Gradient가 커야하고, 트랙 밀도를 높이기 위해서는 Write Head의 Aspect Ratio가 작아져야 한다. 본 연구에서는 3차원 유한 요소법을 이용하여 Write Head의 재료의 자기적 성질과 형상에 따른 고 기록 밀도용 Pole Tip Write Head를 설계하였다.

• Journal of Digital Contents Society
• /
• v.14 no.2
• /
• pp.215-222
• /
• 2013

NAND flash memory-based Solid State Drives (SSD) have lots of merits compared to traditional hard disk drives (HDD). However, random write in SSD is still far slower than sequential read/write and random read. There are two independent approaches to resolve this problem: 1) using part of the flash memory blocks as log blocks, and 2) using internal write buffer (DRAM or Non-Volatile RAM) in SSD. While log blocks are managed by the Flash Translation Layer (FTL), write buffer management has been treated separately from FTL. Write buffer management schemes did not use the exact status of log blocks and log block management schemes in FTL did not consider the behavior of write buffer management scheme. In this paper, we first show that log blocks and write buffer have a tight relationship to each other, which necessitates integrated management of both of them. Since log blocks also can be viewed as another type of write buffer, we can manage both of them as an integrated write buffer. Then we provide three design criteria for the integrated write buffer management scheme which can be very useful to SSD firmware designers.

• Convergence Security Journal
• /
• v.18 no.5_2
• /
• pp.73-82
• /
• 2018

The goal of this study is to look deeper into a read-write education method for improving communication abilities of petty officer majoring students in community colleague level. The read-write education method improves reading and writing abilities at the same time. Therefore, the read-write education method is modified to a 'read-write-correction' education method and the method is planed proper ways to run the course of the education. A writing report class method which is based on 'read-write' education method is the key process of this education. the education method suggests directions of a taking memo and a guideline of summarizing from the reading part, and the directions of a taking memo and a guideline of summarizing are used on report writings class from the writing part of the 'read-write' education method. The correction part of the education method is controlled by instructors under a process of the 'read-write-correction.' The read-write education method by using the report writing helps to improve communication abilities in work fields because the report writing is based on utilizing document formats that can be used future in petty officer work filed. For the last, the study mentions a proposal for further tasks on this field of the study.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.107-110
• /
• 2017

According to researches, while the speed of processor and network in embedded devices is fast enough to meet user requirement, the IO speed is recognized as the main performance bottleneck. Meanwhile it is known that more than 70 percent of IOs are issued from SQLite database. Many researches related SQLite performance optimization is based on WAL mode because WAL mode optimized for write IO performance. In this paper, I propose to optimize SQLite with Atomic Write in the Rollback Journal Mode, which is mainly used in Android and Tizen. I have observed that Atomic Write have a significant write performance improvement(300%) by reducing write, file sync operation and memory usage improvement(80%). Additionally it can block JOJ(Journaling of Journal) and extend the life of the flash memory.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.184-188
• /
• 2014

There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability ($V_{WL,OPT}=1.055V$) as well as to lower the minimum operating voltage for the read and write operations simultaneously ($V_{MIN,READ}=0.58V$, $V_{MIN,WRITE}=0.82V$ for supply voltage $(V_{DD})=1.1V$).

• International journal of advanced smart convergence
• /
• v.12 no.1
• /
• pp.70-75
• /
• 2023

With the recent proliferation of memory-intensive workloads such as deep learning, analyzing memory access characteristics for efficient memory management is becoming increasingly important. Since read and write operations in memory access have different characteristics, an efficient memory management policy should take into accountthe characteristics of thesetwo operationsseparately. Although some previous studies have considered the different characteristics of reads and writes, they require a modified hardware architecture supporting read bits and write bits. Unlike previous approaches, we propose a software-based management policy under the existing memory architecture for considering read/write characteristics. The proposed policy logically partitions memory space into the read/write area and the write area by making use of reference bits and dirty bits provided in modern paging systems. Simulation experiments with memory access traces show that our approach performs better than the CLOCK algorithm by 23% on average, and the effect is similar to the previous policy with hardware support.

• International journal of advanced smart convergence
• /
• v.12 no.4
• /
• pp.164-170
• /
• 2023

With the recent advances in AI (artificial intelligence) and HPC (high-performance computing) technologies, deep learning is proliferated in various domains of the 4th industrial revolution. As the workload volume of deep learning increasingly grows, analyzing the memory reference characteristics becomes important. In this article, we analyze the memory reference traces of deep learning workloads in comparison with traditional workloads specially focusing on read and write operations. Based on our analysis, we observe some unique characteristics of deep learning memory references that are quite different from traditional workloads. First, when comparing instruction and data references, instruction reference accounts for a little portion in deep learning workloads. Second, when comparing read and write, write reference accounts for a majority of memory references, which is also different from traditional workloads. Third, although write references are dominant, it exhibits low reference skewness compared to traditional workloads. Specifically, the skew factor of write references is small compared to traditional workloads. We expect that the analysis performed in this article will be helpful in efficiently designing memory management systems for deep learning workloads.

• Journal of Computing Science and Engineering
• /
• v.8 no.3
• /
• pp.157-172
• /
• 2014

Contemporary embedded systems often use NAND flash memory instead of hard disks as their swap space of virtual memory. Since the read/write characteristics of NAND flash memory are very different from those of hard disks, an efficient page replacement algorithm is needed for this environment. Our analysis shows that temporal locality is dominant in virtual memory references but that is not the case for write references, when the read and write references are monitored separately. Based on this observation, we present a new page replacement algorithm that uses different strategies for read and write operations in predicting the re-reference likelihood of pages. For read operations, only temporal locality is used; but for write operations, both write frequency and temporal locality are used. The algorithm logically partitions the memory space into read and write areas to keep track of their reference patterns precisely, and then dynamically adjusts their size based on their reference patterns and I/O costs. Without requiring any external parameter to tune, the proposed algorithm outperforms CLOCK, CAR, and CFLRU by 20%-66%. It also supports optimized implementations for virtual memory systems.