• Korean Journal of Materials Research
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• v.10 no.12
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• pp.807-811
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• 2000

CeO$_2$ and SrBi$_2$Ta$_2$O$_{9}$ (SBT) thin films for MFISFET (Metal-ferroelectric-insulator-semiconductor-field effect transistor) were deposited by r.f. sputtering and pulsed laser ablation method, respectively. The effects of sputtering gas ratio(Ar:O$_2$) during deposition for CeO$_2$ films were investigated. The CeO$_2$ thin films deposited on Si(100) substrate at $600^{\circ}C$ exhibited (200) preferred orientation. The preferred orientation, Brain size and surface roughness of films decreased with increasing oxygen to argon gas ratio. The films deposited under the condition of Ar:O$_2$= 1 : 1 showed the best C- V characteristics. The leakage current of films showed the order of 10$^{-7}$ ~10$^{-8}$ A at 100kV/cm. The SBT thin films on CeO$_2$/Si substrate showed dense microstructure of polycrystalline phase. From the C-V characteristics of MFIS structure with SBT film annealed at 80$0^{\circ}C$, the memory window width was 0.9V at 5V The leakage current density of Pt/SBT/CeO$_2$/Si structure annealed at 80$0^{\circ}C$ was 4$\times$10$^{-7}$ /$\textrm{cm}^2$ at 5V.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2159-2163
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• 2003

Hand carried computing machinery and tools have been developed into an embedded system which the small footprint operating system is contained internally. Windows CE which is one of imbedded operating system is a lightweight, multithreaded operating system with an optional graphical user interface. Its strength lies in its small size, its Win32 subset API, and its multiplatform support. Therefore we choose to port this OS on Arm based board that is provided high performance, low cost, and low power consumption. In this paper, we describe the architecture of ARM based board, the feature of Windows CE, techniques and steps involved in this porting process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.725-728
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• 2006

본 논문에서는 Embedded 시스템에서 Windows CE 내에 사용되고 있는 불필요한 메모리를 최소화하고 메모리를 좀 더 효율적으로 관리하기 위한 방안으로 가비지컬렉터를 이용한 메모리관리 방법에 대한 연구이다. Embedded 시스템의 힙 메모리 내에 수집할 수 있는 방법 중 전체수집과, 부분수집에 대하여 살펴본다. 가비지컬렉터가 응용 프로그램에서 더 이상 사용하지 않는 힙 내에 개체가 있는지 확인하고, 힙에 대해 사용할 수 있는 메모리가 더 이상 없을 경우 새 연산자가 Out Of Memory Exception를 실행하게 된다. 실험부분에서 가비지컬렉터의 개체사용 여부를 실험한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.670-671
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• 2012

This paper presents a method of constructing telematics terminal embedded architecture for DMB TPEG data service The proposed embedded architecture was designed for terminal. Also, we use WIPI which was used for standard based on mobile middle-ware, and TPEG decoding which was used for Window CE. We can see the advantage compare with previous methods.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.145-145
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• 2000

M-CeO2 (M : noble metal) catalysts have been widely studied as three-way catalysts and methanol synthesis catalysts. Ceria is thought to play a number of roles in these catalysts. The Ce(IV)/Ce(III) redox pair may store/release gases under oxidizing/reducing conditions, extending the operational window. Additionally, metal-ceria interactions lead to several effects, including the dispersion of the active components and promoting the activation of molecules such as CO or NO. Pd is a promising component to current TWC formulations and behaves particularly well when compared with Pt and Rh-based catalysts for low-temperature oxidation of Co and hydrocarbon. However the effect of Pd-ceria interactions on the physicochemical properties of Pd and the redox properties of Ce is not elucidated yet. In order to know exactly about the metal-ceria interactions, the model study are expecting to give a better environment, resulting in the wide use of the surface science tools. The substrate was Si(100) wafer, on which Ta metal was sputtered as a thickness of 100nm. The CeO2 thin film of 30nm was deposited by using the magnetron sputtering. Spin coating and magnetron sputtering methods were used to make the Pd thin film layer. The prepared sample was investigated by in-situ XPS, AES, SEM and AFM analysis.

• Journal of the Korean Chemical Society
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• v.6 no.2
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• pp.155-157
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• 1962

A tiny dust found at the balcony of the Institute indicated about 8,0000 counts per minute by T.G.C.-2 Geiger-Muller tube (1.8mg/$cm^2$ window-thickness) at the distance of 2cm from the window. The main fission fragments, as identified by the present analysis, are 12.5day Ba-140 and 33.1 day Ce-141. The gamma energies were determined using $2"{\times}2"$ NaI(Tl) scintillation detector connected to RCL-256 channel pulse heigt analyzer. The beta energies were evaluated by Feather plot.

• Transactions of the Korean hydrogen and new energy society
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• v.14 no.2
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• pp.155-170
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• 2003

$Cu-Ce/{\gamma}-Al_2O_3$ based catalysts were prepared and tested for selective oxidation of CO in a $H_2$-rich stream(1% CO, 1% $O_2$, 60% $H_2$, $N_2$ as balance). The effects of Cu loading and weight ratio(=Cu/(Cu+Ce)) upon both activity and selectivity were investigated upon the change in temperatures, It was also examined how the activity and selectivity of catalysts were varied with the presence of $CO_2$ and $H_2O$ in the reactant feed. Among the various Cu-Ce catalysts with different catalytic metal composition, Cu-Ce(4 : 16 wf%) /${\gamma}-Al_2O_3$ catalyst showed the highest activity(>$T_{99}$) and selectivities(50-80%) under wide range of temperatures($175-220^{\circ}C$). However, in the Cu-Ce(4 : 16 wt%)/ ${\gamma}-Al_2O_3$, the presence of $CO_2$ and $H_2O$ in the reactant feed decreased the activity and the maximum activity(>$T_{99}$) in terms of reaction temperature moved by about $25^{\circ}C$ toward higher temperature, the $T_{>99}$ window was seen between $210-230^{\circ}C$ (selectivity 50-75%). From $CO_2-/H_2O-TPD$, it can be concluded that the main cause for the decrease in catalytic activity may be attributed to the blockage of the active sites by competitive adsorption of water vapor and $CO_2$ with the reactant at low temperatures.

• Progress in Superconductivity and Cryogenics
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• v.5 no.3
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• pp.11-14
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• 2003

The detailed conditions of dc-sputtering for depositions of yttria-stabilized ZrO$_2$ (YSZ) films were investigated, while the films were grown on the CeO$_2$ template layers on biaxially textured Ni-tapes. The window of oxygen pressures for proper growth of YSZ films, which was dependent on sputtering powers, was determined by sufficient oxidations of the YSZ films and the de-oxidation of the target surface, which was required for rapid sputtering. The window turned out to be fairly wide under certain values of argon pressure. When the sputtering power was raised, the deposition rate increased without narrowing the window. The fabricated YSZ films showed good texture qualities and surface morphologies.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.

• Journal of the Korean Ceramic Society
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• v.37 no.11
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• pp.1051-1057
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• 2000

TiO$_2$와 CeO$_2$박막을 Si 위에 증착한 후 MOCVD법에 의해 PbTiO$_3$박막을 증착하여 MFIS 구조를 형성하였다. 절연층의 후열처리가 절연층 및 MFIS 구조의 전기적 특성에 미치는 영향을 관찰하기 위해 산소분위기와 $600^{\circ}C$~90$0^{\circ}C$의 온도범위에서 후 열처리를 행하였고, C-V 특성 및 누설전류 특성을 분석하였다. CeO$_2$와 TiO$_2$박막의 유전상수는 증착 직후 6.9와 15였으며, 90$0^{\circ}C$ 열처리를 행한 후 약 4.9와 8.8로 감소하였다. 누설전류밀도 역시 증착 직후 각각 7$\times$$10^{-5}$ A/$ extrm{cm}^2$와 2.5$\times$$10^{-5}$ A/$\textrm{cm}^2$에서 90$0^{\circ}C$ 열처리를 거친 후에 약 4$\times$$10^{-8}$ A/$\textrm{cm}^2$와 4$\times$$10^{-9}$ A/$\textrm{cm}^2$로 감소하였다. Ellipsometry 시뮬레이션을 통해 계산된 계면층의 두께는 90$0^{\circ}C$에서 약 115$\AA$(CeO$_2$) 및 140$\AA$(TiO$_2$)까지 증가하였다. 계면층은 MFIS 구조에서 강유전층에 인가되는 전계를 감소시켜 항전계를 증가시켰고, charge injection을 방지하여 Al/PbTiO$_3$/CeO$_2$(90$0^{\circ}C$, $O_2$)/Si 구조의 경우 $\pm$2 V~$\pm$10 V의 측정범위에서 memory window가 계속 증가하는 것을 보여주었다.