• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.903-911
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• 2014

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.7-11
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• 2014

In this paper, we designed resistive MMIC mixer using $0.5{\mu}m$ p-HEMT process. This Mixer is designed to have a similar performance in -4 ~ 4 dBm local oscillator signal power level and to maintain a constant conversion loss and linear performance due to the variation of local signal. In order to have such characteristics, we designed new feedback circuit topology by using FET, and minimized performance change for LO signal power level variation, also obtain MMIC mixer characteristics which is able to apply in wideband. In the design result, When the LO signal power is -4 ~ 4 dBm, there was 6 dB conversion loss and it came up with the excellent result that IIP3 got over 30 dBm in 0.5 ~ 2.6GHz frequency band.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.1-14
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• 1998

In this paper, Antenna, LNA, Mixer, VCO, and Modulation/Demodulation in Baseband processor which are the RF main components in Wireless LAN system for ultra high-speed communications network are studied. Antenna bandwidth and selective fading due to multipath can be major obstacles in high speed digital communications. To solve this problem, wide band MSA which has loop-structure magnetic antenna characteristics is designed. Distributed mixer using dual-gate GaAs MESFET can achieve over 10dB LO/RF isolation without hybrid, and minimize circuit size. As linear mixing signal is produced, distortions can be decreased at baseband signals. Conversion gain is achieved by mixing and amplification simultaneously. Mixer is designed to have wide band characteristics using distributed amplifier. In VCO design, Oscillator design method by large signal analysis is used to produce stable signal. Modulation/Demodulation system in baseband processor, DS/SS technique which is robust against noise and interference is used to eliminate the effect of multipath propagation. DQPSK modulation technique with M-sequences for wideband PN spreading signals is adopted because of BER characteristic and high speed digital signal transmission.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.219-226
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• 2000

In this paper, we design and implement a IF(intermediate frequency) module for WLL(wireless local loop) CDMA(code division multiple access) basestation. The implemented IF transceiver is consists of transmitter, receiver and local oscillator. The considered signal bandwidth is 10 MHz and the local carrier frequency is 40 MHz. As test results, the If transmitter output power is -5dBm $\pm3dB$when the baseband input is -10dBm $\pm3dB$, and the IF receiver output power is -10dBm $\pm3dB$when the IF input is -5dBm $\pm3dB$. Also the AGC(automatic gain control) circuit has dynamic range of 9 dB from -7dBm to +2dBm with output power 2dBm. And the group delay characteristic is analyzed by comparing the phase delay from 1 MHz to 5 MHz and the phase distortion is very low. We can conclude that this IF system can be applied to high speed data rate communication system.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.