• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.143-151
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• 2018

In this paper, a novel hybrid configuration combining a phase-shift full-bridge (PSFB) and a half-bridge resonant LLC converter is proposed for the On-Board Charger of Electric Vehicles (EVs). In the proposed converter, the PSFB converter shares the lagging-leg switches with half-bridge resonant converter to achieve the wide ZVS range for the switches and to improve the efficiency. The output voltage is modulated by the effective-duty-cycle of the PSFB converter. The proposed converter employs an active reset circuit composed of an active switch and a diode for the transformer which makes it possible to achieve zero circulating current and the soft switching characteristic of the primary switches and rectifier diodes regardless of the load, thereby making the converter highly efficient and eliminating the reverse recovery problem of the diodes. In addition an optimal power sharing strategy is proposed to meet the specification of the charger and to optimize the efficiency of the converter. The operation principle the proposed converter and design considerations for high efficiency are presented. A 6.6 kW prototype converter is fabricated and tested to evaluate its performance at different conditions. The peak efficiency achieved with the proposed converter is 97.7%.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.4
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• pp.20-30
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• 2001

A novel 200 MHz CMOS transconductor using translinear cells is proposed. The proposed transconductor consists of voltage followers and current followers based on translinear cells and a resistor. For wide applications, a single-input single-output, a single-Input differential-output, and a fully-differential transconductor are systematically designed, respectively. The theory of operation is described and computer simulation results are used to verify theoretical predictions. The results show that the fully-differential transconductor has a linear input voltage range of ${\pm}2.7$ V, a 3 dB frequency of 200 MHz, and a temperature coefficient of less than 41 $ppm/^{\circ}C$ at supply voltages of ${\pm}3$ V. In order to certify the applicability of the fully-differential transconductor, A ladder-type 3th-order cllitic low pass filter is also designed based on the inductance simulation method. The filter has a ripple bandwidth of 22 MHz, a pass-band ripple of 0.36 dB, and a cutoff frequency of 26 MHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.2
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• pp.328-338
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• 2017

In this paper, a zero torque control scheme adopting current sharing function (CSF) used in integrated Switched Reluctance Motor (SRM) drive with DC battery charger is proposed. The proposed control scheme is able to achieve the keeping position (KP), zero torque (ZT) and power factor correction (PFC) at the same time with a simple novel current sharing function algorithm. The proposed CSF makes the proper reference for each phase windings of SRM to satisfy the total charging current of the battery with zero torque output to hold still position with power factor correction, and the copper loss minimization during of battery charging is also achieved during this process. Based on these, CSFs can be used without any recalculation of the optimal current at every sampling time. In this proposed integrated battery charger system, the cost effective, volume and weight reduction and power enlargement is realized by function multiplexing of the motor winding and asymmetric SR converter. By using the phase winding as large inductors for charging process, and taking the asymmetric SR converter as an interleaved converter with boost mode operation, the EV can be charged effectively and successfully with minimum integral system. In this integral system, there is a position sliding mode controller used to overcome any uncertainty such as mutual inductance or DC offset current sensor. Power factor correction and voltage adaption are obtained with three-phase buck type converter (or current source rectifier) that is cascaded with conventional SRM, one for wide input and output voltage range. The practicability is validated by the simulation and experimental results by using a laboratory 3-hp SRM setup based on TI TMS320F28335 platform.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1187-1195
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• 2013

Photovoltaic inverters should always track the maximum power of solar cell arrays in operation. Also, they should be irrespective of the maximum power point voltage of a wide range of solar cells in tracking the maximum power point. If the current ripple of solar cells occurs, the function of maximum power point tracking drops, and normal tracking is difficult when solar radiation or the maximum power point changes. To solve this problem, this paper proposed a new maximum power point tracking algorithm with high efficiency and an algorithm to reduce the current ripple of solar cells. According to the results from the test on 4KW grid-connected PV inverter, the efficiency of maximum power point tracking and inverter output and the total harmonic distortion of inverter output current showed 99.97%, 97.5% and 1.05% respectively. So, the inverter showed excellent performance, and made possible stable maximum power point tracking operation when the solar radiation rapidly changed from 100% to 10% and from 10% to 100% for 0.5 seconds.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.11
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• pp.1075-1081
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• 2004

In this paper, a VCO of a general advance warning system for vehicle's speed limitation in the X-band used in Japan is designed using a small signal scattering coefficient of PHEMT. A varactor diode that wide tuning range and series resistance 0 H is used for designing the VCO and -85 dBc/Hz of phase noise at 10 kHz of offset frequency is obtained by adjusting the reflection coefficient between the micro-strip line and the varactor device which determines transistor's operation voltage and resonant frequency, In addition +4.5 dBm of basic frequency signal output level and -25.6 dEc of the second harmonic constraint are acquired. Sample that produce in this paper could confirm that more excellent special quality appears than existing products in sensitivity.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.197-201
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• 1997

To realize 10-Gbit/s optical transmission systems, we designed and fabricated a limiting amplifier with extremely high operation frequencies over 10-GHz using AlGaAs/GaAs heterojunction bipolar transistors (HBTs), and investigated their performances. Circuit design and simulation were performed using SPICE and LABRA. A discrete AlGaAs/GaAs HBT with the emitter area of 1.5${\times}$10$\mu\textrm{m}$$^2$, used for the circuit fabrication, exhibited the cutoff frequency of 63GHz and maximum oscillation frequency of 50GHz. After fabrication of MMICs, we observed the very wide bandwidth of DC∼15GHz for a limiting amplifier from the on-wafer measurement. Ceramic-packaged limiting amplifier showed the excellent eye opening, the output voltage swing of 750mV\ulcorner, and the rise/fall time of 40ps, measured at the data rates of 10-Gbit/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.100-108
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• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• Journal of IKEEE
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• v.15 no.4
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• pp.305-312
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• 2011

A primary interest of this work is to develop an efficient and powerful repetitive pulser system for the application of ultra wide band generation. The important component of the pulser system is a small-sized coaxial type spark gap with planar electrodes filled with SF6 gas. A repetitive switching action by the coaxial spark gap generates two consecutive pulses in less than a microsecond with rise times of a few hundred picoseconds (ps). A set of several parameters for the repetitive switching of the spark gap is required to be optimized in charging and discharging systems of the pulser. The parameters in the charging system include a circuit scheme, circuit elements, the applied voltage and current ratings from power supplies. The parameters in the discharging system include the spark gap geometry, electrode gap distance, gas type, gas pressure and the load. The characteristics of the spark gap discharge, such as breakdown voltage, output current pulse and recovery rate are too dynamic to control by switching continuously at a high pulse repetition rate (PRR). This leads to a low charging efficiency of the spark gap system. The breakthrough of the low charging efficiency is achieved by a parallel operation of two spark gaps system. The operational behavior of the two spark gaps system is presented in this paper. The work has focused on improvement of the charging efficiency by scaling the PRR of each spark gap in the two spark gaps system.