• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Journal of IKEEE
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• v.26 no.1
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• pp.50-55
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• 2022

SiC is a power semiconductor with a wide bandgap, high insulation failure strength, and thermal conductivity, but many deep-level defects. Defects that appear in SiC can be divided into two categories, defects that appear in physical properties and interface traps that appear at interfaces. In this paper, Z_1/2 trap concentration 0 ~ 9×10¹⁴ cm^-3 reported at room temperature (300 K) is applied to SiC substrates and epi layer to investigate turn-on characteristics. As the trap concentration increased, the current density, Shockley-read-Hall (SRH), and Auger recombination decreased, and Ron increased by about 550% from 0.004 to 0.022 mohm.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.111-115
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• 2024

Silicon carbide (SiC) has emerged as a promising material for next-generation power semiconductor materials, due to its high thermal conductivity and high critical electric field (~3 MV/cm) with a wide bandgap of 3.3 eV. This permits SiC devices to operate at lower on-resistance and higher breakdown voltage. However, to improve device performance, advanced research is still needed to reduce point defects in the SiC epitaxial layer. This work investigated the electrical characteristics and defect properties using DLTS analysis. Four deep level defects generated by the implantation process and during epitaxial layer growth were detected. Trap parameters such as energy level, capture-cross section, trap density were obtained from an Arrhenius plot. To investigate the impact of defects on the device, a 2D TCAD simulation was conducted using the same device structure, and the extracted defect parameters were added to confirm electrical characteristics. The degradation of device performance such as an increase in on-resistance by adding trap parameters was confirmed.

• Korean Journal of Materials Research
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• v.20 no.12
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• pp.676-680
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• 2010

Most TCOs such as ITO, AZO(Al-doped ZnO), FTO(F-doped $SnO_2$) etc., which have been widely used in LCD, touch panel, solar cell, and organic LEDs etc. as transparent electrode material reveal n-type conductivity. But in order to realize transparent circuit, transparent p-n junction, and introduction of transparent p-type materials are prerequisite. Additional prerequisite condition is optical transparency in visible spectral region. Oxide based materials usually have a wide optical bandgap more than ~3.0 eV. In this study, single-phase transparent semiconductor of $SrCu_2O_2$, which shows p-type conductivity, have been synthesized by 2-step solid state reaction at $950^{\circ}C$ under $N_2$ atmosphere, and single-phase $SrCu_2O_2$ thin films of p-type TCOs have been deposited by RF magnetron sputtering on alkali-free glass substrate from single-phase target at $500^{\circ}C$, 1% $H_2$/(Ar + $H_2$) atmosphere. 3% $H_2$/(Ar + $H_2$) resulted in formation of second phases. Hall measurements confirmed the p-type nature of the fabricated $SrCu_2O_2$ thin films. The electrical conductivity, mobility of carrier and carrier density $5.27{\times}10^{-2}S/cm$, $2.2cm^2$/Vs, $1.53{\times}10^{17}/cm^3$ a room temperature, respectively. Transmittance and optical band-gap of the $SrCu_2O_2$ thin films revealed 62% at 550 nm and 3.28 eV. The electrical and optical properties of the obtained $SrCu_2O_2$ thin films deposited by RF magnetron sputtering were compared with those deposited by PLD and e-beam.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.25 no.4
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• pp.127-134
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• 2015

Aluminum nitride (AlN) single crystals have attracted much attention for a next-generation semiconductor application because of wide bandgap (6.2 eV), high thermal conductivity ($285W/m{\cdot}K$), high electrical resistivity (${\geq}10^{14}{\Omega}{\cdot}cm$), and high mechanical strength. The bulk AlN single crystals or thin film templates have been mainly grown by PVT (sublimation) method, flux method, solution growth method, and hydride vapor phase epitaxy (HVPE) method. Since AlN suffers difficulty in commercialization due to the defects that occur during single crystal growth, crystalline quality improvement via defects analyses is necessary. Etch pit density (EPD) analysis showed that the growth misorientations and the defects in the AlN surface exist. Transmission electron microscopy (TEM) and electron back-scattered diffraction (EBSD) analyses were employed to investigate the overall crystalline quality and various kinds of defects. TEM studies show that the morphology of the AlN is clearly influenced by stacking fault, dislocation, second phase, etc. In addition EBSD analysis also showed that the zinc blende polymorph of AlN exists as a growth defects resulting in dislocation initiator.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.74-74
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• 2010

One-dimensional nanosturctures such as nanowires and nanotube have been mainly proposed as important components of nano-electronic devices and are expected to play an integral part in design and construction of these devices. Silicon carbide(SiC) is one of a promising wide bandgap semiconductor that exhibits extraordinary properties, such as higher thermal conductivity, mechanical and chemical stability than silicon. Therefore, the synthesis of SiC-based nanowires(NWs) open a possibility for developing a potential application in nano-electronic devices which have to work under harsh environment. In this study, one-dimensional nanowires(NWs) of cubic phase silicon carbide($\beta$-SiC) were efficiently produced by thermal chemical vapor deposition(T-CVD) synthesis of mixtures containing Si powders and hydrocarbon in a alumina boat about $T\;=\;1400^{\circ}C$ SEM images are shown that the temperature below $1300^{\circ}C$ is not enough to synthesis the SiC NWs due to insufficient thermal energy for melting of Si Powder and decomposition of methane gas. However, the SiC NWs are produced over $1300^{\circ}C$ and the most efficient temperature for growth of SiC NWs is about $1400^{\circ}C$ with an average diameter range between 50 ~ 150 nm. Raman spectra revealed the crystal form of the synthesized SiC NWs is a cubic phase. Two distinct peaks at 795 and $970\;cm^{-1}$ over $1400^{\circ}C$ represent the TO and LO mode of the bulk $\beta$-SiC, respectively. In XRD spectra, this result was also verified with the strongest (111) peaks at $2{\theta}=35.7^{\circ}$, which is very close to (111) plane peak position of 3C-SiC over $1400 ^{\circ}C$ TEM images are represented to two typical $\beta$-SiC NWs structures. One is shown the defect-free $\beta$-SiC nanowire with a (111) interplane distance with 0.25 nm, and the other is the stacking-faulted $\beta$-SiC nanowire. Two SiC nanowires are covered with $SiO_2$ layer with a thickness of less 2 nm. Moreover, by changing the flow rate of methane gas, the 300 sccm is the optimal condition for synthesis of a large amount of $\beta$-SiC NWs.

• Korean Journal of Materials Research
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• v.33 no.12
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• pp.525-529
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• 2023

β-Ga₂O₃ has become the focus of considerable attention as an ultra-wide bandgap semiconductor following the successful development of bulk single crystals using the melt growth method. Accordingly, homoepitaxy studies, where the interface between the substrate and the epilayer is not problematic, have become mainstream and many results have been published. However, because the cost of homo-substrates is high, research is still mainly at the laboratory level and has not yet been scaled up to commercialization. To overcome this problem, many researchers are trying to grow high quality Ga₂O₃ epilayers on hetero-substrates. We used diluted SiH4 gas to control the doping concentration during the heteroepitaxial growth of β-Ga₂O₃ on c-plane sapphire using metal organic chemical vapor deposition (MOCVD). Despite the high level of defect density inside the grown β-Ga₂O₃ epilayer due to the aggregation of random rotated domains, the carrier concentration could be controlled from 1 × 10¹⁹ to 1 × 10¹⁶ cm^-3 by diluting the SiH4 gas concentration. This study indicates that β-Ga₂O₃ hetero-epitaxy has similar potential to homo-epitaxy and is expected to accelerate the commercialization of β-Ga₂O₃ applications with the advantage of low substrate cost.