• Title/Summary/Keyword: Whirlpool

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An Integrated Cryptographic Processor Supporting ARIA/AES Block Ciphers and Whirlpool Hash Function (ARIA/AES 블록암호와 Whirlpool 해시함수를 지원하는 통합 크립토 프로세서 설계)

  • Kim, Ki-Bbeum;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.22 no.1
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    • pp.38-45
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    • 2018
  • An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

A Hardware Implementation of Whirlpool Hash Function using 64-bit datapath (64-비트 데이터패스를 이용한 Whirlpool 해시 함수의 하드웨어 구현)

  • Kwon, Young-Jin;Kim, Dong-Seong;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.485-487
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    • 2017
  • The whirlpool hash function adopted as an ISO / IEC standard 10118-3 by the international standardization organization is an algorithm that provides message integrity based on an SPN (Substitution Permutation Network) structure similar to AES block cipher. In this paper, we describe the hardware implementation of the Whirlpool hash function. The round block is designed with a 64-bit data path and encryption is performed over 10 rounds. To minimize area, key expansion and encryption algorithms use the same hardware. The Whirlpool hash function was modeled using Verilog HDL, and simulation was performed with ModelSim to verify normal operation.

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A Hardware Implementation of Whirlpool Hash Function using Cortex-M0 (Cortex-M0를 이용한 Whirlpool 해시함수의 하드웨어 구현)

  • Kim, Dong-seong;Shin, Kyung-wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2018.05a
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    • pp.166-168
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    • 2018
  • 본 논문에서는 Whirlpool 해시 코어가 Cortex-M0의 슬레이브로 인터페이스된 보안 SoC 프로토타입 구현에 대해 기술한다. ISO/IEC에서 표준으로 채택된 경량 해시 알고리듬인 Whirlpool 해시 함수를 64-비트의 데이터 패스로 구현하였으며, 키 확장 연산과 암호화 연산을 수행하는 하드웨어를 공유하여 면적이 최소화되도록 설계하였다. 설계된 보안 SoC 프로토타입을 Cyclone-V FPGA에 구현한 후, ULINK2 어댑터와 Cortex 내부 디버거를 통해 Whirlpool 해시 코어에서 연산된 해시값을 확인함으로써 SoC 프로토타입의 동작을 확인했다.

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A Cortex-M0 based Security System-on-Chip Embedded with Block Ciphers and Hash Function IP (블록암호와 해시 함수 IP가 내장된 Cortex-M0 기반의 보안 시스템 온 칩)

  • Choe, Jun-Yeong;Choi, Jun-Baek;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.23 no.2
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    • pp.388-394
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    • 2019
  • This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

An Efficient Hardware Implementation of Whirlpool Hash Function (Whirlpool 해쉬 함수의 효율적인 하드웨어 구현)

  • Park, Jin-Chul;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.263-266
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    • 2012
  • This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

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Security Analysis of the Whirlpool Hash Function in the Cloud of Things

  • Li, Wei;Gao, Zhiyong;Gu, Dawu;Ge, Chenyu;Liao, Linfeng;Zhou, Zhihong;Liu, Ya;Liu, Zhiqiang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.1
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    • pp.536-551
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    • 2017
  • With the advancement and deployment of leading-edge telecommunication technologies for sensing and collecting, computing related information, Cloud of Things (CoTs) has emerged as a typical application platform that is envisioned to revolutionize the daily activities of human society, such as intelligent transportation, modern logistics, food safety, environmental monitoring, etc. To avoid any possible malicious attack and resource abuse, employing hash functions is widely recognized as one of the most effective approaches for CoTs to achieve message integrity and data authentication. The Whirlpool hash function has served as part of the joint ISO/IEC 10118-3 International Standard by the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC). In this paper, we propose an effective differential fault analysis on Whirlpool in the byte-oriented random fault model. The mathematical analysis and experimental results show that 8 random faults on average are required to obtain the current 512-bit message input of whirlpool and the secret key of HMAC-Whirlpool. Our work demonstrates that Whirlpool and HMAC-Whirlpool are both vulnerable to the single byte differential fault analysis. It provides a new reference for the security analysis of the same structure of the hash functions in the CoTs.

An Unified Security Processor Implementation of Block Ciphers and Hash Function (블록암호와 해시함수의 통합 보안 프로세서 구현)

  • Kim, Ki-Bbeum;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.250-252
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    • 2017
  • 블록암호 국제표준 AES(Advanced Encryption Standard), 국내표준 ARIA(Academy, Research Institute, Agency) 및 국제표준 해시함수 Whirlpool을 통합 하드웨어로 구현하였다. ARIA 블록암호와 Whirlpool 해시함수는 AES와 유사한 구조를 가지며, 본 논문에서는 저면적 구현을 위해서 하드웨어 자원을 공유하여 설계하였다. Verilog-HDL로 설계된 ARIA-AES-Whirlpool 통합 보안 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였고, $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 20 MHz의 동작 주파수에서 71,872 GE로 구현되었다.

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The properties of noise and vibration in Whirlpool bath and plan for its reduction (공동주택 월풀욕조의 소음진동 특성 및 저감 방안)

  • Bae, Sang-Hwan;Lee, Byung-Kwon
    • Proceedings of the SAREK Conference
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    • 2005.11a
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    • pp.506-510
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    • 2005
  • This study shows work on the properties of noise and vibration in Whirlpool bath and plan for its reduction. Totally through 3 steps. we found out the properties of noise and vibration. various anti-vibration design for an effeciency test is conducted. By Anti-vibration for the pump causing vibration, about 4dB(A) was reduced. Moreover. by anti-vibration construction fixing the bathtub frame. about 3db(A) could be reduced. In the case of anti-vibration construction about the wall around the bathtub. and spreading damping paint on the bathtub. the noise was reduced.

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Management Model-Buildings of Location Conflict on Crematory Facilities (화장장시설에 관한 입지갈등 관리모형 구축)

  • Lee, Man-Hyung;Lee, Joong-Hoon;Kwon, Hyuk-Il
    • Korean System Dynamics Review
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    • v.8 no.1
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    • pp.67-95
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    • 2007
  • This paper focuses on prototype management models of location conflict concerned with crematory facilities in Korea. Using causal loops and stock-flow diagrams, it examines behavioral patterns of key variables, which would contribute to developing objective evaluation criteria. After a series of simulation works, the paper finds that the top priority should be given to how to improve neighboring residents' perception, ahead of specific compensation issues. Otherwise, they are open to vicious cycles or impasse. Juxtaposing individual cases together, Pusan and Cheongju examples which experienced the extreme confrontation in the initial stage could succeed in resolving crematory location conflict, especially between local residents and the public authorities, as the latter has repeatedly guaranteed to the former higher standards of participation. The opposite was almost true for Seoul and Ulsan cases, both of which were drawn into a crematory location whirlpool, incrementally losing resident's participation base. These results imply that the proposed management models would enhance mutual understanding among major stake-holders in relatively a shorter time, not to mention the overall cost.

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The 3D numerical analysis on runway with the flow in direction perpendicular to the runway (활주로 방향에 수직인 유동이 활주로에 미치는 영향에 대한 3차원 수치해석)

  • Hong, Gyo-Young;Sheen, Dong-Jin
    • Journal of Advanced Navigation Technology
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    • v.14 no.4
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    • pp.479-488
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    • 2010
  • The aim of this paper is to research the change in the turbulent flow and the AOA occurred by the wind perpendicular to the direction of runway according to the three-dimensional numerical analysis. The maximum amplitude of AOA variation on runway reached $6^{\circ}$ within 1 second because of the wake formed by the constructions in the vicinity of the airport. The overall effects appeared in aperiodic forms. It was also observed the rapid flow generated between the buildings shifted into the existing wake and eventually merged with it. It is expected thai the strong wake will cause instability during takeoff and landing.