• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2005.05a
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• pp.395-400
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• 2005

Nano-scale fabrication of silicon substrate based on the use of atomic force microscopy (AFM) was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate by a simple scratching process, has been applied instead of conventional silicon cantilever for scanning. A thin damaged layer forms in the substrate at the diamond tip-sample junction along scanning path of the tip. The damaged layer withstands against wet chemical etching in aqueous KOH solution. Diamond tip acts as a patterning tool like mask film for lithography process. Hence these sequential processes, called tribo-nanolithography, TNL, can fabricate 2D or 3D micro structures in nanometer range. This study demonstrates the novel fabrication processes of the micro cantilever and diamond tip as a tool for TNL using micro-patterning, wet chemical etching and CVD. The developed TNL tools show outstanding machinability against single crystal silicon wafer. Hence, they are expected to have a possibility for industrial applications as a micro-to-nano machining tool.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.8 s.185
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• pp.39-46
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• 2006

Nano-scale fabrication of silicon substrate based on the use of atomic force microscopy (AFM) was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate by a simple scratching process, has been applied instead of conventional silicon cantilever for scanning. A thin mask layer forms in the substrate at the diamond tip-sample junction along scanning path of the tip. The mask layer withstands against wet chemical etching in aqueous KOH solution. Diamond tip acts as a patterning tool like mask film for lithography process. Hence these sequential processes, called tribo-nanolithography, TNL, can fabricate 2D or 3D micro structures in nanometer range. This study demonstrates the novel fabrication processes of the micro cantilever and diamond tip as a tool for TNL using micro-patterning, wet chemical etching and CVD. The developed TNL tools show outstanding machinability against single crystal silicon wafer. Hence, they are expected to have a possibility for industrial applications as a micro-to-nano machining tool.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.7 s.172
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• pp.71-78
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• 2005

The purpose of this study is to suggest a hyperfine maskless writing technique by using the nanoindentation and HF wet etching technique. Indents were made on the surface of Pyrex7740 glass by the hyperfine indentation process with a Berkovich diamond indenter, and they were etched in $50\;wr\%$ HF solution. After etching process, convex structure was obtained due to the deformation-induced hillock phenomena. In this study, effects of indentation process parameters (etching time, normal load, loading .ate, hold-time at the maximum load) on the morphologies of the indented surfaces after isotopic etching were investigated from an angle of deformation energies. Finally, sample characters were written to show the possibility of the application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1075-1079
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• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• Transactions of Materials Processing
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• v.12 no.7
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• pp.640-646
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• 2003

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as potential application to fabricate the surface nanostructures because of its operational versatility and simplicity. The objective of the work is to suggest new mastless pattern fabrication technique using the combination of machining by nanoindenter and KOH wet etching. The scratch option of the nanoindenter is a very promising method for obtaining nanometer scale features on a large size specimen because it has a very wide working area and load range. Sample line patterns were machined on a silicon surface, which has a native oxide on it, by constant load scratch (CLS) of the Nanoindenter with a Berkovich diamond tip, and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structure was made because of masking effect of the affected layer generated by nano-scratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved patterns can be used as a mold that will be used for mass production processes such as nanoimprint or PDMS molding process. All morphological data of scratch traces were scanned using atomic force microscope (AFM).

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.863-866
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• 2008

For the cost reduction in the fabrication of display panels, a reverse moving system was equipped to a compacted in-line wet etch/cleaning system. For the effect of the alternating movement of substrate on the wet etch process, ITO layers were etched in various moving modes of substrates and the results were compared and analyzed.

• Korean Journal of Materials Research
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• v.29 no.11
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• pp.697-702
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• 2019

In this study, using a wet chemical process, we evaluate the effectiveness of different solution concentrations in removing layers from a solar cell, which is necessary for recovery of high-purity silicon. A 4-step wet etching process is applied to a 6-inch back surface field(BSF) solar cell. The metal electrode is removed in the first and second steps of the process, and the anti-reflection coating(ARC) is removed in the third step. In the fourth step, high purity silicon is recovered by simultaneously removing the emitter and the BSF layer from the solar cell. It is confirmed by inductively coupled plasma mass spectroscopy(ICP-MS) and secondary ion mass spectroscopy(SIMS) analyses that the effectiveness of layer removal increases with increasing chemical concentrations. The purity of silicon recovered through the process, using the optimal concentration for each process, is analyzed using inductively coupled plasma atomic emission spectroscopy(ICP-AES). In addition, the silicon wafer is recovered through optimum etching conditions for silicon recovery, and the solar cell is remanufactured using this recovered silicon wafer. The efficiency of the remanufactured solar cell is very similar to that of a commercial wafer-based solar cell, and sufficient for use in the PV industry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.3
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• pp.143-147
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• 2017

To evaluate surface characteristics and improve crystalline quality of AlN single crystal grown by physical vapor transport (PVT) method, wet chemical etching process using $KOH/H_2O_2$ mixture in a low temperature condition and thermal annealing process was proceeded respectively. Conventional etching process using strong base etchant at a high temperature (above $300^{\circ}C$) had formed over etching phenomenon according to crystalline quality of materials. When it occurred to over etching phenomenon, it had a low reliability of dislocation density because it cannot show correct number of etch pits per estimated area. Therefore, it was proceeded to etching process in a low temperature (below $100^{\circ}C$) using $H_2O_2$ as an oxidizer in KOH aqueous solution and to be determined optimum etching condition and dislocation density via scanning electron microscope (SEM). For improving crystalline quality of AlN single crystal, thermal annealing process was proceeded. When compared with specimens as-prepared and as-annealed, full width at half maximum (FWHM) of the specimen as-annealed was decreased exponentially, and we analyzed the mechanism of this process via double crystal X-ray diffraction (DC-XRD).

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.319.1-319.1
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• 2016

Recently, the Al-doped ZnO (ZnO:Al) films are intensively used in thin film a-Si solar cell applications due to their high transmittance and good conductivity. The textured ZnO:Al films are used to enhance the light trapping in thin film solar cells. The wet etch process is used to texture ZnO:Al films by dipping in diluted acidic solutions like HCl or HF. During that process the glass substrate could be damaged by the acidic solution and it may be difficult to apply it for the inline mass production process since it has to be done outside the chamber. In this paper we report a new technique to control the surface morphology of RF-sputtered ZnO:Al films. The ZnO:Al films are textured with vaporized HF formed by the mixture of HF and H2SiO3 solution. Even though the surface of textured ZnO:Al films by vapor etching process showed smaller and sharper surface structures compared to that of the films textured by wet etching, the haze value was dramatically improved. We achieved the high haze value of 78% at the wavelength of 540 nm by increasing etching time and HF concentration. The haze value of about 58% was achieved at the wavelength of 800 nm when vapor texturing was used. The ZnO:Al film texture by HCl had haze ratio of about 9.5 % at 800 nm and less than 40 % at 540 nm. In addition to low haze ratio, the texturing by HCl was very difficult to control etching and to keep reproducibility due to its very fast etching speed.