• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 하계학술대회 논문집 B
• /
• pp.1354-1356
• /
• 2000

This paper deals with a 300kV dc charging system to be used ?s a voltage source in a circuit breaker synthetic short-circuit-test facility. Cockcroft-walton circuit is used to step up the rectified voltage from a single phase transformer of which primary winding is hooked up to an ac220 wall plug. Two systems with the same ratings have been designed and manufactured. The two system have been made of different supporting structure with different insulating materials. The paper describes a couple of charging schemes, system configurations and the synthetic test circuit in which the developed system is to be used.

• Journal of Information Display
• /
• 제2권2호
• /
• pp.39-44
• /
• 2001

The conditions of the wall charges and priming particles in a unit discharge cell in AC PDP seriously affect the addressing discharge characteristics in the driving method with ramped setup pulse. Moreover, the discharge conditions at the end of the scan line may be different from the first scan line because of the difference of about 1ms address time. Consequently, the addressing time and its dispersion may be different for any two discharge cells that lead to misfiring and the increase in the total addressing time. In order to improve the addressing time and its dispersion, we have applied different addressing voltage at each cell such as progressively increase pulse voltage instead of constant one. As a result, the addressing time and its dispersion of all cells were improved by about 30% compared with the conventional driving method.

• 한국전기전자재료학회논문지
• /
• 제25권11호
• /
• pp.906-909
• /
• 2012

The address discharge characteristics of a open dielectric structure compared with the conventional panel structure are investigated by measuring the discharge firing voltage. The open dielectric structure could easily produce the discharge between the scan and the sustain electrodes by erasing the dielectric layer between two electrodes. Due to the changes in the discharge firing characteristics of the open dielectric structure between the two sustain electrodes, the conventional reset waveform including the address waveform needs to be modified. The modified driving waveform suitable for the open dielectric structure is proposed and examined in AC PDP.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
• /
• pp.1053-1056
• /
• 2008

The effects of wall charge and bias voltage on exo-electron emission currents were examined. In addition, the effects of doping elements on the currents were investigated. These results indicated that the statistical delay is inversely proportional to the exo-electron emission currents measured.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2003년도 제24회 학술발표회 초록집
• /
• pp.225-225
• /
• 2003

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
• /
• pp.1552-1553
• /
• 2006

A thermionic gun of injector linac for pohang accelerator laboratory is required to generate beam pulse width less than 1 nsec. The gun uses cathode-grid assembly(EIMAC Y824) and operates up to 80 kV anode voltage. In order research characteristics of the electron gun, emission current from gun wear measured by the wall current monitor. In this paper the pulser system and characteristics of the emission current in region from 30 mA to 15 A are described.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 추계학술대회 논문집
• /
• pp.522-522
• /
• 2007

We observed new physical phenomia. The dispersion relation and the distributions of RF electric field in the corrugated wall waveguide are analyzed numerically. The measurement of the dispersion relation are obsered by a plunger method employed in the slow wave structure for linear accelerators.

• Journal of information and communication convergence engineering
• /
• 제14권1호
• /
• pp.40-44
• /
• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.

• 한국표면공학회지
• /
• 제28권3호
• /
• pp.182-191
• /
• 1995

A highly porous silicon layer was fabricated by anodizing single crystalline silicon in a dilute solution of hydrofluoric acid. The color of the porous silicon changed from red and blue to yellow gold during the anodizing process. The current-voltage (I-V) curve of the anodizing process showed a typical Schottky diode rectification form. The cell voltage decreased with the increase of HF concentration in the solution at high current range. However, the voltage was independent on HF concentration in the solution at low current range. The pore size was dependant on anodizing condition (HF concentration, current and anodizing time). The pore size and wall width of porous silicon layer were 4~6 and 1~3 nm, respectively. Surface of the porous silicon was covered with silicon compound ($SiH_x$etc.) according to IR spectrum analysis. The peak wavelength and width of photoluminescence (PL) spectrum of porous silicon were 650~850 nm (1.5~1.9 eV) and 250 nm, respectively. The photoluminescence intensity and peak wavelength, and porosity of porous silicon increased with increasing anodizing current and decreased with increasing HF concentration in the anodizing solution.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
• /
• pp.162-162
• /
• 1999

초고주파 집적회로의 핵심소자로 각광을 받고 있는 GaAs MESFET(MEtal-emiconductor)은 게이트 형성 공정이 가장 중요하며, WNx 내화금속을 이용한 planar 게이트 구조의 경우 임계전압(Vth:threshold voltage)의 균일도가 우수할 뿐만 아니라 특히 Side-wall을 이용한 self-align 게이트는 소오스 저항을 줄일 수 있어 고성능의 소자 제작을 가능하게 한다.(1) 본 연구의 핵심이 되는 Side-wall을 형성하기 위하여 PECVD법에 의한 SiOx 박막을 증착하고, 건식식각법을 이용하여 SiOx side-wall을 형성하였다. 이 공정을 이용하여 소오스 저항이 낮고 임계전압의 균일도가 우수한 고성능의 self-aligned gate MESFET을 제작하였다. 3inch GaAs 기판상에 이온주입법에 의한 채널 형성, d.c. 스퍼터링법에 의한 WNx 증착, PECVD법에 의한 SiOx 증착, MERIE(Magnetic Enhanced Reactive Ion Etcing)에 의한 Side-wall 형성, LDD(Lightly Doped Drain)와 N+ 이온주입, 그리고 RTA(Rapid Thermal Annealing)를 사용하여 활성화 공정을 수행하였다. 채널은 40keV, 4312/cm2로, LDD는 50keV, 8e12/cm2로 이온주입하였고, 4000A의 SiOx를 증착한 후 2500A의 Side-wall을 형성하였다. 옴익 접촉은 AuGe/Ni/Au 합금을 이용하였고, 소자의 최종 Passivation은 SiNx 박막을 이용하였다. 제작된 소자의 전기적 특성은 hp4145B parameter analyzer를 이용한 전압-전류 측정을 통하여 평가하였다. Side-wall 형성은 0.3$\mu\textrm{m}$ 이상의 패턴크기에서 수직으로 잘 형성되었고, 본 연궁에서는 게이트 길이가 0.5$\mu\textrm{m}$인 MESFET을 제작하였다. d.c. 특성 측정 결과 Vds=2.0V에서 임계전압은 -0.78V, 트랜스컨덕턴스는 354mS/mm, 그리고 포화전류는 171mA/mm로 평가되었다. 특히 본 연구에서 개발된 트랜지스터의 게이트 전압 변화에 따른 균일한 트랜스 컨덕턴스의 특성은 RF 소자로 사용할 때 마이크로 웨이브의 왜곡특성을 없애주기 때문에 균일한 신호의 전달을 가능하게 한다. 0.5$\mu\textrm{m}$$\times$100$\mu\textrm{m}$ 게이트 MESFET을 이용한 S-parameter 측정과 Curve fitting 으로부터 차단주파수 fT는 40GHz 이상으로 평가되었고, 특히 균일한 트랜스컨덕턴스의 경향과 함께 차단주파수 역시 게이트 바이어스, 즉 소오스-드레스인 전류의 변화에 따라 균일한 값을 보였다. 본 연구에서 개발된 Side-wall 공정은 게이트 길이가 0.3$\mu\textrm{m}$까지 작은 경우에도 사용가능하며, WNx self-align gate MEESFET은 낮은 소오스저항, 균일한 임계전압 특성, 그리고 높고 균일한 트랜스 컨덕턴스 특성으로 HHP(Hend-Held Phone) 및 PCS(Personal communication System)와 같은 이동 통신용 단말기의 MMICs(Monolithic Microwave Integrates Circuits)의 제작에 활용될 것으로 기대된다.