• Composites Research
• /
• v.27 no.5
• /
• pp.183-189
• /
• 2014

Experimental considerations have been performed to obtain the clear optical microscopic images of graphene oxide which are useful to probe its quality and morphological information such as a shape, a size, and a thickness. In this study, we investigated the contrast enhancement of the optical images of graphene oxide after hydrazine vapor reduction on a Si substrate coated with a 300 nm-thick $SiO_2$ dielectric layer. Also, a green-filtered light source gave higher contrast images comparing to optical images under standard white light. Furthermore, it was found that a image channel separation technique can be an alternative to simply identify the morphological information of graphene oxide, where red, green, and blue color values are separated at each pixels of the optical image. The approaches performed in this study can be helpful to set up a simple and easy protocol for the morphological identification of graphene oxide using a conventional optical microscope instead of a scanning electron microscopy or an atomic force microscopy.

• Journal of the Microelectronics and Packaging Society
• /
• v.6 no.4
• /
• pp.1-7
• /
• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.36 no.1
• /
• pp.18-26
• /
• 2016

The semiconductor industry is one of the key industries of Korea, which has continued growing at a steady annual growth rate. Important technology for the semiconductor industry is high integration of devices. This is to increase the memory capacity for unit area, of which key is photolithography. The photolithography refers to a technique for printing the shadow of light lit on the mask surface on to wafer, which is the most important process in a semiconductor manufacturing process. In this study, the width and step-height of wafers patterned through this process were measured to ensure uniformity. The widths and inter-plate heights of the specimens patterned using photolithography were measured using transmissive digital holography. A transmissive digital holographic interferometer was configured, and nine arbitrary points were set on the specimens as measured points. The measurement of each point was compared with the measurements performed using a commercial device called scanning electron microscope (SEM) and Alpha Step. Transmission digital holography requires a short measurement time, which is an advantage compared to other techniques. Furthermore, it uses magnification lenses, allowing the flexibility of changing between high and low magnifications. The test results confirmed that transmissive digital holography is a useful technique for measuring patterns printed using photolithography.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.7
• /
• pp.1227-1234
• /
• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Applied Chemistry for Engineering
• /
• v.34 no.5
• /
• pp.522-528
• /
• 2023

In this work, adhesive tapes were prepared for the dicing process in semiconductor manufacturing. Compounds with different numbers of photoreactive groups (f = 1 to 3) were synthesized and incorporated into acrylic copolymers to formulate UV-curable acrylic adhesives. Structural confirmation of the synthesized photoreactive compounds (f = 2 or 3) was performed using nuclear magnetic resonance (NMR) spectroscopy. The introduction of the photoreactive compounds into the acrylic adhesive was accomplished by urethane reactions, and the successful synthesis of the UV-curable acrylic adhesive was verified by Fourier transform infrared (FT-IR) measurements. To evaluate the performance of the adhesive, the peel strength was evaluated before and after UV irradiation using a silicon wafer as a substrate. The adhesive exhibited high peel strength (~2000 gf/25 mm) before UV exposure, which was significantly reduced (~5 gf/25 mm) after UV exposure. Interestingly, the adhesive containing multifunctional photoreactive compounds showed the most significant reduction in peel strength. In addition, surface residue measurements by field emission scanning electron microscopy (FE-SEM) showed minimal surface residue (~0.2%) after UV exposure. Overall, these results contribute to the understanding of the behavior of UV-curable acrylic adhesives and pave the way for potential applications in semiconductor manufacturing processes.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.30 no.1
• /
• pp.33-39
• /
• 2020

Lightweight geopolymers were fabricated by using fused slag from integrated gasification combined cycle as a law material and Si sludge from silicon wafer process as a bloating material for the purpose of replacing autoclaved lightweight concrete (ALC). Density and compressive strength of geopolymers were measured and compared with the properties of ALC according to the variation of mol concentration of alkaline activator, W/S ratio, addition of fibers, and addition of polystyrene and the possibility of replacing ALC panel was estimated through the comparisons. Although the geopolymer satisfying the standard of ALC panel was not made by controlling mol concentration and W/S ratio, addition of inserts such as fibers and polystyrene insert was tried to overcome the obstacle of enhancing properties. Geopolymers cannot satisfying the standard of ALC panel by adding carbon or glass fibers; however, adding fibers can be suggested as one of the methods enhancing compressive strength because the compressive strength of the specimen containing 0.3 wt.% glass fibers was increased by 3 times. The maximum addition of polystyrene insert was turned out to be 50 vol.% and the properties of geopolymers varied by the method of insertion. When using single polystyrene insert, compressive strength was 17.8 MPa and density was 0.996 g/㎤ which were similar values to the standard of ALC panel. If the difficulties of reproductivity of production and insertion method of inserts were overcome through the future research, the geopolymers containing polystyrene inserts could possibly replace ALC panel.

• Korean Journal of Materials Research
• /
• v.10 no.9
• /
• pp.601-606
• /
• 2000

Nickel mono-silicide(NiSi) shows no increase of resistivity as the line width decreases below 0.15$\mu\textrm{m}$. Furthermore, thin silicide can be made easily and restrain the redistribution of dopants, because NiSi in created through the reaction of one nickel atom and one silicon atom. Therefore, we investigated the deposition condition of Ni films, heat treatment condition and basic properties of NiSi films which are expected to be employed for sub-0.15$\mu\textrm{m}$ class devices. The nickel silicide film was deposited on the Si wafer by using a dc-magnetron sputter, then annealed at the temperature range of $150~1000^{\circ}C$. Surface roughness of each specimen was measured by using a SPM (scanning probe microscope). Microstructure and qualitative composition analysis were executed by a TEM-EDS(transmission electron microscope-energy dispersive x-ray spectroscope). Electrical properties of the materials at each annealing temperature were measured by a four-point probe. As the results of our study, we may conclude that; 1. SPM can be employed as a non-destructive process to monitor NiSi/NiSi$_2$ transformation. 2. For annealing temperature over $800^{\circ}C$, oxygen pressure $Po_2$ should be kept below $1.5{\times}10^{-11}torr$ to avoid oxidation of residual Ni. 3. NiSi to $NiSi_2$ transformation temperature in our study was $700^{\circ}C$ from the four-point probe measurement.

• Journal of the Microelectronics and Packaging Society
• /
• v.17 no.3
• /
• pp.79-84
• /
• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Journal of Sensor Science and Technology
• /
• v.23 no.3
• /
• pp.185-191
• /
• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.24 no.6
• /
• pp.573-580
• /
• 2004

The main goal of this study was to develop a micro-fabrication process for the capacitive micromachined ultrasonic transducer (cMUT). In order to achieve this goal, the former research results of the micro-electro-mechanical system (MEMS) process for the cMUT were analyzed. The membrane deposition, sacrificial layer deposition and etching were found to be a main process of fabricating the cMUT. The optimal conditions for those microfabrication were determined by the experiment. The thickness, uniformity, and residual stress of the $Si_3N_3$ deposition which forms the membrane of the cMUT were characterized after growing the $Si_3N_3$ on Si-wafer under various process conditions. As a sacrificial layer, the growth rate of the $SiO_2$ deposition was analyzed under several process conditions. The optimal etching conditions of the sacrificial layer were analyzed. The microfabrication process developed in this study will be used to fabricate the cMUT.