• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1065-1068
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• 2003

The nano imprint process is one of the next generation lithography has been mentioned as one of major nanoreplication techniques because it is simple process, low cost, high replication fidelity and relatively high throughput. This process requires a surface contact between a template with patterns and a wafer on a stage. After contact, the vertical moving the template to the wafer causes some directional motions of the stage. Thus the stage must move according to the motions of the template to avoid the damage of the transferred patterns on the wafer. This study is to develop the wafer stage with a passive compliance to overcome the damage. This stage is designed with the concept like that it has a monolithic, symmetry and planar 6-DOF mechanism.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.134-142
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• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.81-86
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• 2023

Recently, there has been an increased demand for light-emitting diode (LED) due to the growing emphasis on environmental protection. However, the use of GaN-based sapphire in LED manufacturing leads to the generation of defects, such as dislocations caused by lattice mismatch, which ultimately reduces the luminous efficiency of LEDs. Moreover, most inspections for LED semiconductors focus on evaluating the luminous efficiency after packaging. To address these challenges, this paper aims to detect defects at the wafer stage, which could potentially improve the manufacturing process and reduce costs. To achieve this, image processing and deep learning-based defect detection techniques for Sapphire Epi-Wafer used in Green LED manufacturing were developed and compared. Through performance evaluation of each algorithm, it was found that the deep learning approach outperformed the image processing approach in terms of detection accuracy and efficiency.

• KSTLE International Journal
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• v.5 no.2
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• pp.37-43
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• 2004

Abstract : Nano/micro-scale friction properties were investigated on Si (100) and three self-assembled monolayers (SAMs) (PFOTC, DMDM, DPDM) coated on Si-wafer by chemical vapor deposition technique. Experiments were conducted at ambient temperature(24$pm$1$circ$C) and humidity(45$pm$5%). Friction at nano-scale was measured using Atomic Force Microscopy (AFM) in the range of 0-40nN normal loads. In both Si-wafer and SAMs, friction increased linearly as a function of applied normal load. Results showed that friction was affected by the inherent adhesion in Ssi-wafer, and in the case of SAMs the physical/chemical structures had a major influence. Coefficient of friction of these test samples at the micro-scale was also energies. In order to study the effect of contact area on coefficient of friction at the micro-scale, friction was measured for Si-wafer and DPDM against Soda Lime balls (Duke Scientiffic Corporation) of different radii (0.25 mm, 0.5 mm and 1 mm) at different applied normal loads (1500, 3000 and 4800 mN). Results showed that Si-wafer had higher coefficient of friction than DPDM. Further, unlike that in the case of DPDM, friction in Si-wafer was severely influenced by its wear. SEM evidences showed that solid-solid adhesion was the wear mechanism in Si-wafer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Transactions of the Society of Information Storage Systems
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• v.2 no.2
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• pp.96-99
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• 2006

In this research, a wafer-level transfer method of cantilever away on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Korean Journal of Materials Research
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• v.32 no.9
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• pp.396-402
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• 2022

In this study, surface roughness and interfacial defect characteristics were analyzed after forming a high-k oxide film on the surface of a prime wafer and a test wafer, to study the possibility of improving the quality of the test wafer. As a result of checking the roughness, the deviation in the test after raising the oxide film was 0.1 nm, which was twice as large as that of the Prime. As a result of current-voltage analysis, Prime after PMA was 1.07 × 10 A/cm² and Test was 5.61 × 10 A/cm², which was about 5 times lower than Prime. As a result of analyzing the defects inside the oxide film using the capacitance-voltage characteristic, before PMA Prime showed a higher electrical defect of 0.85 × 10¹² cm^-2 in slow state density and 0.41 × 10¹³ cm^-2 in fixed oxide charge. However, after PMA, it was confirmed that Prime had a lower defect of 4.79 × 10¹¹ cm^-2 in slow state density and 1.33 × 10¹² cm^-2 in fixed oxide charge. The above results confirm the difference in surface roughness and defects between the Test and Prime wafer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1119-1122
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• 2004

In the UV-NIL process using an elementwise patterned stamp (EPS), which includes channels formed to separate each element with patterns, low-viscosity resin droplets with a nano-liter volume are dispensed on all elements of the EPS. Following pressing of the EPS, the EPS is illuminated with UV light to cure the resin; and then the EPS is separated from several thin patterned elements on a wafer. Experiments on UV-NIL were performed on an EVG620-NIL. 50 － 70 nm features of the EPS were successfully transferred to 4 in. wafers. Especially, the wafer deformation during imprint was analyzed using the finite element method (FEM) in order to study the effect of the wafer deformation on the UV-NIL using EPS.

• IE interfaces
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• v.16 no.3
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• pp.344-351
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• 2003

Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

• Tribology and Lubricants
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• v.17 no.3
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• pp.191-197
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• 2001

Nano adhesion and friction characteristics between SPM(scanning electron microscope) tips and flat plates of different materials were experimentally studied. Tests were performed to measure adhesion and friction in AFM(atomic force microscope) and LFM(lateral force microscope) modes in different conditions of relative humidity. Three different Si$_3$N$_4$ tips (rdaii : 15nm, 22nm and 50 nm) and three different flat plates of Si-wafer(100), W-DLC(tungsten-incorporated diamond-like carbon) and DLC were used. Results generally showed that adhesion and friction increased with the tip radius, and W-DLC and DLC surfaces were superior to Si-wafer. But the adhesion force of Si-wafer showed non linearity with the tip radius while W-DLC and DLC surfaces showed good correlation to the “JKR model”. It was found that high adhesion force between Si-wafer and a large radius of tip was caused by a capillary action due to the condensed water.