• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.433-433
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• 2012

As the requirement in patterning geometry continuously shrinks down, the termination of etch process at the exact time became crucial for the success in nano patterning technology. By virtue of real-time optical emission spectroscopy (OES), etch end point detection (EPD) technique continuously develops; however, it also faced with difficulty in low open ratio etching, typically in self aligned contact (SAC) and one cylinder contact (OCS), because of very small amount of optical emission from by-product gas species in the bulk plasma glow discharge. In developing etching process, one may observe that coupon test is being performed. It consumes costs and time for preparing the patterned sample wafers every test in priority, so the coupon wafer test instead of the whole patterned wafer is beneficial for testing and developing etch process condition. We also can observe that etch open area is varied with the number of coupons on a dummy wafer. However, this can be a misleading in OES study. If the coupon wafer test are monitored using OES, we can conjecture the endpoint by experienced method, but considering by data, the materials for residual area by being etched open area are needed to consider. In this research, we compare and analysis the OES data for coupon wafer test results for monitoring about the conditions that the areas except the patterns on the coupon wafers for real-time process monitoring. In this research, we compared two cases, first one is etching the coupon wafers attached on the carrier wafer that is covered by the photoresist, and other case is etching the coupon wafers on the chuck. For comparing the emission intensity, we chose the four chemical species (SiF2, N2, CO, CN), and for comparing the etched profile, measured by scanning electron microscope (SEM). In addition, we adopted the Dynamic Time Warping (DTW) algorithm for analyzing the chose OES data patterns, and analysis the covariance and coefficient for statistical method. After the result, coupon wafers are over-etched for without carrier wafer groups, while with carrier wafer groups are under-etched. And the CN emission intensity has significant difference compare with OES raw data. Based on these results, it necessary to reasonable analysis of the OES data to adopt the pre-data processing and algorithms, and the result will influence the reliability for relation of coupon wafer test and whole wafer test.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2004년도 춘계학술대회 학술발표 논문집 제14권 제1호
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• pp.149-152
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• 2004

Generally the wafer is increased by 300mm. We are desired that the wafer is prevented from pollutions of metal contaminant on surface of wafer. We have to develop new wafer cleaning process of IC Manufacturing that can reduce DI water and chemical by removal of the wafer cleaning process step. Moreover, it is difficult to control temprature and density of chemical in spite of rapidly increasing automation of system. We design smart module controller for new generation of semiconductor wet station with intelligent algorithm using data that is taken by computer simulation for optimal system.

• 반도체디스플레이기술학회지
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• 제2권2호
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• 대한전자공학회논문지
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• 제25권6호
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• pp.647-653
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• 1988

A rapid thermal annealing system using tungsten halogen lamp has been designed and assembled. A control scheme where the temperature control is executed with calculated wafer temperature by considering the thermocouple delay rather than measured thermocouple temperature,is proposed. This control scheme gives more accurate control of the wafer temperature. In addition, the distribution of transmitted light power to the wafer in the system has been simulated, and lamp interval modification has been able to give more uniform light power distribution. Considering incident light spectrum, absorption, reflection, radiation of silicon, etc., temperature profile has been simulated. When the light power uniformity on the 3" wafer is below 1%, the temperature uniformity is about 2%.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1999년도 추계학술대회 논문집 - 한국공작기계학회
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• pp.502-506
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• 1999

Recently, the miniature of electric products such as notebook, cellular-phone etc. is apparently appeared, due to the smaller size of the semiconductor chips. As the size of chip gets smaller, the circuit could be easily damaged by the slightest influence, so it is important to control the chipping generation in the process of dicing. This paper deals with chipping of the silicon wafer dicing. The relationships between the dicing force and the wafer chipping are investigated. It is confirmed that the wafer chipping increases as the dicing force increases.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.61-67
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• 2014

Micro-cracks in crystalline silicon wafer often result in wafer breakage in solar wafer manufacturing, and also their existence may lead to electrical failure in post fabrication inspection. Therefore, the reliable detection of micro-cracks is of importance in the photovoltaic industry. In this paper, an experimental method to select optimal parameters in anisotropic diffusion filter is proposed. It can reliably detect micro-cracks by the distinct extension of boundary as well as noise reduction in near-infrared image patterns of micro-cracks. Its performance is verified by experiments of several type cracks machined.

• 반도체디스플레이기술학회지
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• 제3권3호
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• pp.5-9
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• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• 한국세라믹학회지
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• 제36권8호
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• 전기학회논문지
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• 제60권7호
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• pp.1434-1437
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• 2011

Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

• 한국멀티미디어학회논문지
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• 제16권6호
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• pp.782-794
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• 2013

본 논문에서는 카메라를 이용한 웨이퍼 위치 인식 알고리즘을 제안한다. 먼저 챔버 외부의 조명 반사와 카메라로 인한 영상의 원근 왜곡을 제거하기 위하여 투영 변환을 적용하여 실제 웨이퍼와 같이 정원의 형태로 복원한다. 다음, 에지 검출 알고리즘을 이용하여 웨이퍼의 외부 경계를 추출한 후, 일반화 대칭 변환을 적용하여 원을 검출함으로서 웨이퍼의 위치를 검사한다. 일반화 대칭 변환은 영상에서 화소쌍들 사이의 대칭값을 거리 가중치 함수, 위상 가중치 함수, 화소들의 기울기 크기와 로그 맵핑이 결합되어 영상에서 관심 영역을 추출한다. 제안하는 방법을 적용하여 웨이퍼가 올바른 위치에 장착되었는가를 검사하여 클리닝 시스템 장비와 웨이퍼의 파손을 미연에 방지한다.