• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.88-138
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• 1996

Electronics grew up to the largest industry in the world supported by Si wafer. In near future, the Si wafer may use 300mm in diameter for economic requirement. This size wafer may use to produce large logic chip, 256Mbit DRAM, and other large complex and high density chip. Then, the quality including flatness and crustal characters may be required very high performance. And, their price should be reasonable and high quantity may be required. These requirements should be solve lot of hard problems of crystal growth, wafering mechanical processing and their cost problems. In this presentation, I may discuss following items.

• Industrial Engineering and Management Systems
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• v.4 no.1
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• pp.47-53
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• 2005

The efficiency of fabrication (fab) operation is one of the key factors in order for a semiconductor manufacturing company to stay competitive. Optimization of manpower and forecasting manpower needs in a modern fab is an essential part of the future strategic planing and a very important to the operational efficiency. As the semiconductor manufacturing technology has entered the 8-inch wafer era, the complexity of fab operation increases with the increase of wafer size. The wafer handling method has evolved from manual mode in 6-inch wafer fab to semi-automated or fully automated factory in 8-inch and 12-inch wafer fab. The distribution of manpower requirement in each specialty varied as the trend of fab operation goes for downsizing manpower with automation and outsourcing maintenance work. This paper is to study the specialty distribution of manpower from the requirement in a typical 6-inch, 8-inch to 12-inch wafer fab. The human resource planning in today’s fab operation shall consider many factors, which include the stability of technical talents. This empirical study mainly focuses on the human resource planning, the manpower distribution of specialty structure and the forecast model of internal demand/supply in current semiconductor manufacturing company. Considering the market fluctuation with the demand of varied products and the advance in process technology, the study is to design a headcount forecast model based on current manpower planning for direct labour (DL) and indirect labour (IDL) in Taiwan’s fab. The model can be used to forecast the future manpower requirement on each specialty for the strategic planning of human resource to serve the development of the industry.

• Journal of Environmental Health Sciences
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• v.37 no.1
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• pp.12-21
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• 2011

The objective of this study is to review retrospective exposure assessment methods used in wafer fabrication operations to determine whether adverse health effects including mortality or cancer incidence are related to employment in particular work activities and to recommend an appropriate approach for retrospective exposure assessment methods for epidemiological study. The goal of retrospective exposure assessment for such studies is to assign each study subject to a workgroup in such a way that differences in exposure within the workgroups are minimized, as well as to maximize the contrasts in exposure between workgroups. To reduce the misclassification of exposure and to determine if adverse health effects including mortality or cancer incidence are related to particular work activities of wafer fabrication workers, a minimum requirement of work history information on the wafer manufacturing eras, job and department at which they were exposed should be assessed. Retrospective assessment of the task that semiconductor workers performed should be conducted to determine not only the effect of a particular job on the development of adverse health effects including mortality or cancer incidence, but also to adjust for the healthy worker effect. In order to identify specific hazardous agents that may cause adverse health effects, past exposure to a specific agent or agent matrices should also be assessed.

• Journal of Mechanical Science and Technology
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• v.20 no.12
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• pp.2025-2033
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• 2006

This paper presents, the design of a latch mechanism for wafer containers in a standard mechanical interface environment. For an integrated circuits fabrication factory, the standard mechanical interfaced wafer container is an effective tool to prevent wafers from particle contamination during wafer storage, transporting or transferring. The latch mechanism inside the container door is used to latch and further seal the wafer container for safety and air quality. Kinematic characteristics of the mechanism are established by analyzing the required functions of the mechanisms. Based on these characteristics, a methodology for enumerating feasible latch mechanisms is developed. New mechanisms with one degree-of-freedom and up to five links are generated. An optimum design is also identified with respect to the criteria pertinent to the application. The computer-aided simulation is also built to verify the design.

• International Journal of Precision Engineering and Manufacturing
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• v.7 no.3
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• pp.35-38
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• 2006

A study of electrowetting using an Octadecyltrichlorosilane (OTS) self-assembled monolayer (SAM) and Z- Tetraol 2000 perfluoropolyether lubricant as hydrophobic layers on Si and $SiO_2$ wafer was performed. The $SiO_2$ layer used as insulating layer was thermally grown on the silicon wafer to a thickness of 220-230 nm. The results demonstrated that the contact angle decreased from $100^{\circ}$ to $80^{\circ}$ at 28 V applied potential on $SiO_2$ wafer coated with OTS and the contact angle appeared to be reversible. However, the contact angle on the $SiO_2$ wafer coated with Z- Tetraol 2000 was not observable at 28 V applied potential. Furthermore, the contact angle on the Si wafer coated with OTS or Z- Tetraol 2000 appeared to be irreversible due to the generation of electrolysis in the droplet. It is concluded that it is feasible to use SAM as a hydrophobic layer in electrowetting applications.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.277-278
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.1265-1266
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• 2013

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1378-1383
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• 2003

A ferroelectric (called piezoelectric afterwards) wafer has been widely used as a key component of actuators or sensors of a layer type. According to recent researches, the piezoelectric wafer behaves in a nonlinear way under excessive electro-mechanical loadings. In the present paper, one-dimensional constitutive equations for the nonlinear behavior of a piezoelectric wafer are proposed based on the principles of thermodynamics and a simple viscoplasticity theory. The predictions of the developed model are compared with experimental observations.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.433-435
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• 1987

Thermal reoxidation was carried out to eliminate hole traps at the surface of Si wafer. As the result, the good surface state of wafer was obtained and hole traps were eliminate at the inversion layer. For the evaluation of reoxidation effects. MOS diode was fabricated and its C-Y curve was plotted.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.