• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.213-230
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• 2005

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.51-52
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• 2003

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.23-28
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• 2009

We investigated the wafer-level MEMS capping process for which cavity formation in Si wafer was not required. Ni caps were formed by electrodeposition on 4" Si wafer and Ni rims of the Ni caps were bonded to the Cu rims of bottom Si wafer by using epoxy. Then, top Si wafer was debonded from the Ni cap structures by using SnBi layer of low melting temperature. As-evaporated SnBi layer was composed of double layers of Bi and Sn due to the large difference in vapor pressures of Bi and Sn. With keeping the as-evaporated SnBi layer at $150^{\circ}C$ for more than 15 sec, SnBi alloy composed of eutectic phase and Bi-rich $\beta$ phase was formed by interdiffusion of Sn and Bi. Debonding between top Si wafer and Ni cap structures was accomplished by melting of the SnBi layer at $150^{\circ}C$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.124-128
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• 2001

We apply for the first time a low cost and loss wafer level packaging technology for RF-MEMS device. The proposed structure was simulated by finite element method (FEM) tool (HFSS of Ansoft). S-parameter measured of the package shows the return loss (S11) of 20dB and the insertion loss (S21) of 0.05dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1029-1034
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• 2012

This paper presents a cost-effective and high-performance film bulk acoustic resonator (FBAR) duplexer module for US-PCS handset applications. The FBAR device uses a glass wafer level packaging process, which is a more cost-effective alternative to the typical silicon capping process. The maximum insertion losses of the FBAR duplexer at the Tx and Rx bands are of 1.9 and 2.4 dB, respectively. The total thickness of the duplexer module is 1.2 mm, including the glass-wafer bonded Tx/Rx FBAR devices, PCB board, and transfer molding material.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.03b
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• pp.35-50
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• 2002

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.71-74
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• 2013

In this study, the effects of wafer warpage on the misalignment during wafer stacking process were investigated. The wafer with $45{\mu}m$ bow height warpage was purposely fabricated by depositing Cu thin film on a silicon wafer and the bonding misalignment after bonding was observed to range from $6{\mu}m$ to $15{\mu}m$. This misalignment could be explained by a combination of $5{\mu}m$ radial expansion and $10{\mu}m$ linear slip. The wafer warpage seemed to be responsible for the slip-induced misalignment instead of radial expansion misalignment.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)