• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.11-15
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• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.129-133
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• 2001

In this paper, hermetic sealing was studied fur wafer level packaging of the MEMS devices. With the flip-chip bonding method, this B-stage epoxy sealing will be profit to MEMS device sealing and further more RF-MEMS device sealing. B-stage epoxy can be cured 2-step and hermetic sealing can be obtained. After defining $500{\mu}{\textrm}{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was then aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line were maintained during the sealing process. The height of the seal-line was controlled within $\pm0.6${\mu}{\textrm}{m}$ and the strength was measured to about 20MPa by pull test. The leak rate of the epoxy was about $10^7$ cc/sec from the leak test.

• Journal of Sensor Science and Technology
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• v.13 no.6
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• pp.430-435
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• 2004

The resolution of the accelerometer, fabricated with MEMS technology is mainly affected by mechanical and electrical noise. To reduce mechanical noise, we have to increase mass of the structure part and quality factor related with the degree of vacuum packaging. On the other hand, to increase mass of the structure part, the thickness of the structure must be increased and ICP-RIE is used to fabricate the high aspect ratio structure. At this time, footing effect make the sensitivity of the accelerometer decreasing. This paper presents a hybrid SOG(Silicon On Glass) Process to fabricate a lateral silicon accelerometer with differential capacitance sensing scheme which has been designed and simulated. Using hybrid SOG Process, we could make it a real to increase the structural thickness and to prevent the footing effect by deposition of metal layer at the bottom of the structure. Moreover, we bonded glass wafer to structure wafer anodically, so we could realize the vacuum packaging at wafer level. Through this way, we could have an idea of controlling of quality factor.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.231-247
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• 2005

• The Journal of Korea Robotics Society
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• v.2 no.3
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• pp.249-254
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• 2007

본 논문에서는 웨이퍼 레벨 밀봉 실장된 수직 운동 가속도 신호를 감지할 수 있는 초소형 Z축 가속도 센싱 엘리먼트를 제작하였다. 초소형 Z축 가속도 센싱 엘리먼트는 수직 방향의 정전용량 변화를 필요로 하기 때문에 단일 기판상에 수직 단차의 형성을 가능케 하는 확장된 희생 몸체 미세 가공 기술 (Extended Sacrificial Bulk Micromachining, ESBM) 을 이용하여 제작되었다. 확장된 희생 몸체 미세 가공 기술을 이용하면 정렬오차가 없이 상하부 양쪽에 수직 단차를 갖는 실리콘 구조물의 제작이 가능하다. 또한, MEMS 센싱 엘리먼트의 부유된 실리콘 구조물을 보호하기 위하여 웨이퍼 레벨 밀봉 실장 기술이 적용하여 고신뢰성, 고수율, 고성능의 Z축 가속도 센서를 제작하였다. 신호 처리 회로와 가속도 센서를 결합하여 Z축 가속도 센싱 시스템을 제작하였고 운동가속도 범위 10 g 이상, 정지 드리프트 17.3 mg 그리고 대역폭 60 Hz 이상의 성능을 나타내었다.

• Transactions of the Society of Information Storage Systems
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• v.2 no.3
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• pp.163-168
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• 2006

Small form factor optical pickup (SFFOP) corresponding to BD specifications is strongly proposed for the next-generation portable storage device. In order to generate SFFOP, small sized optical pickup has been fabricated. We have developed a small sited optical pickup that is called the integrated optical pickup (IOP). The fabrication method of this system is mainly dependant on the use of the wafer based micro fabrication technology, which has been used in MEMS process such as photolithography, reactive ion etching, wafer bonding, and packaging process. This approach has the merits for mass production and high assembling accuracy. In this study, to generate the small sized optical pickup for high recording capacity, IOP corresponding to BD specifications has been designed and developed, including three main parts, 1) design, fabrication and evaluation of objective lens unit, 2) design and fabrication of IOP and 3) evaluation process of FES and TES.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.1
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• pp.58-66
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• 2005

Inertial-grade vertical-type and lateral-type differential resonant accelerometers (DRXLs) are designed, fabricated using one process and tested for navigational applications. The accelerometers consist of an out-of-plane (for z-axis) accelerometer and in-plane (for x, y-axes) accelerometers. The sensing principle of the accelerometer is based on gap-sensitive electrostatic stiffness changing effect. It says that the natural frequency of the accelerometer can be changed according to an electrostatic force on the proof mass of the accelerometer. The out-of-plane resonant accelerometer shows bias stability of $2.5{\mu}g$, sensitivity of 70 Hz/g and bandwidth of 100 Hz at resonant frequency of 12 kHz. The in-plane resonant accelerometer shows bias stability of $5.2{\mu}g$, sensitivity of 128 Hz/g and bandwidth of 110 Hz at resonant frequency of 23.4 kHz. The measured performances of two accelerometers are suitable for an application of inertial navigation.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.49-53
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• 2018

Recently, technologies for integrating various devices such as a flexible device, a transparent device, and a MEMS device have been developed. The key processes of heterogeneous device manufacturing technology are chip or wafer-level bonding process, substrate grinding process, and thin substrate handling process. In this study, the effect of Si substrate grinding process on the electrical properties of tin oxide thin films applied as transparent thin film transistor or flexible electrode material was investigated. As the Si substrate thickness became thinner, the Si d-spacing decreased and strains occurred in the Si lattice. Also, as the Si substrate thickness became thinner, the electric conductivity of tin oxide thin film decreased due to the lower carrier concentration. In the case of the thinner tin oxide thin film, the electrical conductivity was lower than that of the thicker tin oxide thin film and did not change much by the thickness of Si substrate.