• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• 반도체디스플레이기술학회지
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• 제3권3호
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• pp.5-9
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• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 The IMAPS-Korea Workshop 2000 Emerging Technology on Packaging
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• pp.55-85
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• 2000

MEMS(Micro Electro Mechanical System) technology. MEMS Inertial Sensors promise a new wide market for many areas -Challenge. significant cost reduction by wafer level packaging and testing. decreasing of power consumption by miniaturization. enhancing of performance and reliability. on-chip integration for multiplicity. MEMS is newly emerging technology.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.124-128
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• 2001

We apply for the first time a low cost and loss wafer level packaging technology for RF-MEMS device. The proposed structure was simulated by finite element method (FEM) tool (HFSS of Ansoft). S-parameter measured of the package shows the return loss (S11) of 20dB and the insertion loss (S21) of 0.05dB.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.23-28
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• 2009

Si 기판의 캐비티 형성이 불필요한 웨이퍼-레벨 MEMS capping 공정을 연구하였다. 4인치 Si 웨이퍼에 Ni 캡을 전기도금으로 형성하고 Ni 캡 rim을 Si 하부기판의 Cu rim에 에폭시 본딩한 후, SnBi debonding 층을 이용하여 상부기판을 Ni 캡 구조물로부터 debonding 하였다. 진공증착법으로 형성한 SnBi debonding 층은 Bi와 Sn 사이의 심한 증기압 차이에 의해 Bi/Sn의 2층 구조로 이루어져 있었다. SnBi 증착 층을 $150^{\circ}C$에서 15초 이상 유지시에는 Sn과 Bi 사이의 상호 확산에 의해 eutectic 상과 Bi-rich $\beta$상으로 이루어진 SnBi 합금이 형성되었다. $150^{\circ}C$에서 유지시 SnBi의 용융에 의해 Si 기판과 Ni 캡 구조물 사이의 debonding이 가능하였다.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 춘계학술발표대회 및 제12회 신소재 심포지엄
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• pp.14.2-14.2
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• 2007

• 마이크로전자및패키징학회지
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• 제15권2호
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• pp.29-36
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• 2008

본 연구에서는 MEMS 소자의 직접화 및 소형화에 필수적인 through-wafer via interconnect의 신뢰성 문제를 연구하였다. 이를 위하여 Au-Sn eutectic 접합 기술을 이용하여 밀봉(hermetic) 접합을 한 웨이퍼 레벨 MEMS 패키지 소자를 개발하였으며, 전기도금법을 이용하여 수직 through-hole via 내부를 구리로 충전함으로써 전기적 연결을 시도하였다. 제작된 MEMS 패키지의 크기는 $1mm{\times}1mm{\times}700{\mu}m$이었다. 제작된 MEMS패키지의 신뢰성 수행 결과 비아 홀(via hole)주변의 크랙 발생으로 패키지의 파손이 발생하였다. 구리 through-via의 기계적 신뢰성에 영향을 줄 수 있는 여러 인자들에 대해서 수치적 해석 및 실험적인 연구를 수행하였다. 분석 결과 via hole의 크랙을 발생시킬 수 있는 파괴 인자로서 열팽창 계수의 차이, 비아 홀의 형상, 구리 확산 현상 등이 있었다. 궁극적으로 구리 확산을 방지하고, 전기도금 공정의 접합력을 향상시킬 수 있는 새로운 공정 방식을 적용함으로써 비아 홀 크랙으로 인한 패키지의 파괴를 개선할 수 있었다.

• 마이크로전자및패키징학회지
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• 제10권3호
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• pp.57-65
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• 2003

본 연구에서는 웨이퍼 레벨 진공 패키징된 MEMS자이로스코프 소자의 신뢰성 시험 및 분석을 통하여 웨이퍼 레벨 진공 패키징의 파괴 메카니즘을 연구하였다. 진공 패키징의 주된 파괴 모드는 누설, 가스투과, 그리고 outgassing이다. 누설은 접합 계면이나 재질의 결함을 통하여 주로 발생되며, 접합폭을 증가시키거나 단결정 실리콘을 사용하면 누설이 감소한다. Outgassing은 실리콘 및 유리기판의 표면 및 내부에서 발생하며 주로 $H_2O$와, $CO_2$, $C_3H_5$ 및 유기 오염물질이었다. Epi-poly의 경우 SOI 웨이퍼보다 약 10배의 outgassing을 발생시킨다. 또한 유리기판을 샌드블라스트 공정을 사용하여 가공한 경우, 약 2.5배의 outgassing 양이 증가한다. Outgassing 제거를 위해서는 접합 전에 웨이퍼를 pre-baking하는 과정이 필수적이며, outgassing의 발생을 최대로 하기 위한 최적의 pre-baking조건은 실리콘과 유리 웨이퍼를 $400^{\circ}C$와 $500^{\circ}C$ 사이에서 pre-baking하는 것이다.

• 센서학회지
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• 제15권1호
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• pp.58-64
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• 2006

In this study, we describe a low-temperature wafer-level thermocompression bonding using electroplated gold seal line and bonding pads by electroplating method for RF-MEMS devices. Silicon wafers, electroplated with gold (Au), were completely bonded at $320^{\circ}C$ for 30 min at a pressure of 2.5 MPa. The through-hole interconnection between the packaged devices and external terminal did not need metal filling process and was made by gold films deposited on the sidewall of the throughhole. This process was low-cost and short in duration. Helium leak rate, which is measured to evaluate the reliability of bonded wafers, was $2.7{\pm}0.614{\times}10^{-10}Pam^{3}/s$. The insertion loss of the CPW packaged was $-0.069{\sim}-0.085\;dB$. The difference of the insertion loss between the unpackaged and packaged CPW was less than -0.03. These values show very good RF characteristics of the packaging. Therefore, gold thermocompression bonding can be applied to high quality hermetic wafer level packaging of RF-MEMS devices.