• Journal of Mechanical Science and Technology
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• 제20권9호
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• pp.1492-1501
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• 2006

A transportation system of single wafer has been developed to be applied to semiconductor manufacturing process of the next generation. In this study, the experimental apparatus consists of two kinds of track, one is for propelling a wafer, so called control track, the other is for generating an air film to transfer a wafer, so called transfer track. The wafer transportation speed has been evaluated by the numerical and the experimental methods for three types of nozzle position a..ay (i.e., the front-, face- and rear-array) in an air levitation system. Test facility for 300mm wafer has been equipped with two control tracks and one transfer track of 1500mm length from the starting point to the stopping point. From the present results, it is found that the experimental values of the wafer transportation speed are well in agreement with the computed ones. Namely, the computed values of the maximum wafer transportation speed $V_{max}$ are slightly higher than the experimental ones by about $15{\times}20%$. The disparities in $V_{max}$ between the numerical and the experimental results become smaller as the air velocity increases. Also, at the same air flow rate, the order of wafer transportation speeds is : $V_{max}$ for the front-array > $V_{max}$ for the face-array > $V_{max}$ for the rear-array. However, the face-array is rather more stable than any other type of nozzle array to ensure safe transportation of a wafer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권4호
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• 산업경영시스템학회지
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• 제38권4호
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.

• 한국시뮬레이션학회논문지
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• 제19권4호
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• pp.99-109
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• 2010

기존의 반도체 생산 공장에서 운용되는 공정설비의 자동화된 웨이퍼 이송을 위한 스케줄링 운용전략에 대한 연구는 일반적으로 특정 공정 환경과 시스템 형태에서 운용되는 이송패턴에 최적화시킨 규칙기반으로 진행되어 왔다. 그러나 이러한 방식은 시스템이나 공정이 달라지면 새로운 규칙이 필요하거나 전체 운용 전략을 변경해야 하는 문제가 발생할 수 있다. 또한, 규칙이 추가될수록 확장, 유지 보수 시에 추가된 규칙들의 상호 연관 작용에 대한 고려가 부족한 경우 예기치 않은 문제를 유발할 시킬 수 있는 위험성을 내포하고 있다. 따라서 본 논문에서는 이러한 문제점을 개선하기 위해 이송패턴이나 설비의 형태에 일반적으로 적용 가능한 동적 우선순위 기반의 기본 이송작업 선택 알고리즘을 제시하였다. 또한 특수한 요구 사항에 대해서는 범용성을 저하시키지 않는 범위 내에서의 최소한의 규칙 처리부를 별도로 관리하는 방식으로 운용 환경 변화에 일관된 스케줄링 정책을 유지하고 확장 시의 안정성 저하를 최소화하여 생산성 향상을 이끌 수 있는 범용 스케줄링 알고리즘을 제안하였다. 이에 대한 검증을 위하여 트윈 슬롯 형태의 반도체 공정설비를 대상으로 모델링 및 시뮬레이션 환경을 구축하였고, 시뮬레이션을 통해 타당성을 검증하였다.

• 대한기계학회논문집A
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• 제34권12호
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• pp.1857-1863
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• 2010

본 논문에서는 탄소나노튜브 필름을 이용한 투명 압저항체의 제작 및 특성 연구를 수행하였다. 진공필터 방식으로 제작된 다양한 투과도를 가지는 탄소나노튜브 필름은 금층이 증착된 실리콘 기판위에서 사진식각 공정을 통해 패터닝이 된 후, 금층과 실리콘 기판의 약한 접착력으로 인해 실리콘 러버인 poly-dimethysiloxane (PDMS) 로 전사된다. 탄소나노튜브 필름의 압저항 특성을 분석하기 위해, 얇은 PDMS 멤브레인의 처짐에 대한 탄소나노튜브 필름의 저항 변화를 측정하여 10-20 의 개이지 팩터를 얻었으며, 인가 압력에 대한 저항 변화 실험을 수행하였다. 본 실험을 통하여 탄소나노튜브 필름은 폴리머 멤스의 다양한 응용분야에 투명한 압저항체로 사용될 수 있을 것으로 판단한다.

• 한국생산제조학회지
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• 제22권5호
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• pp.831-836
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• 2013

This study demonstrates the process of fabricating patterns using tribonanolithography (TNL),with laboratory-made micro polycrystalline diamond (PCD) tools that are attached to an atomic force microscope (AFM). The various patterns are easily fabricated using mechanical scratching, under various normal loads, using the PCD tool on single crystal silicon, which is the master mold for replication in this study. Then, polydimethylsiloxane (PDMS) replica molds are fabricated using precise pattern transfer processes. The transferred patterns show high dimensional accuracy as compared with those of TNL-processed silicon micro molds. TNL can reduce the need for high cost and complicated apparatuses required for conventional lithography methods. TNL shows great potential in that it allows for the rapid fabrication of duplicated patterns through simple mechanical micromachining on brittle sample surfaces.

• 전자공학회논문지D
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• 제35D권5호
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• pp.54-62
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• 1998

In a plasma etching system, ions become an important parameter in determining the wafer topography which depends on both the physical sputtering mechanism and the chemically enhanced reaction. this paper reports the energy and angular distributions of ions across the plasma sheath using a monte carlo method. The ion distribution is mainly affected by the magnitude of the sheath voltage and by the collision in the sheath. Furthemore, the local potential distribution in a plamsa sheath has been determined by solving the poisson's equation. In th is work, ionic collisions were cosidered in terms of both charge exchange and momentum transfer. The three-dimensional distributions of ions were calculated with varying the input process conditions in the plasma reactor.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.158-158
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• 2012

A new kind of organic-inorganic hybrid polymer, poly(tetraphenyl)silole siloxane (PSS), was invented and synthesized for realization of its unique charge trap properties. The organic portions consisting of (tetraphenyl)silole rings are responsible for electron trapping owing to their low-lying LUMO, while the Si-O-Si inorganic linkages of high HOMO-LUMO gap provide the intrachain energy barrier for controlling electron transport. Such an alternation of the organic and inorganic moieties in a polymer may give an interesting quantum well electronic structure in a molecule. The PSS thin film was fabricated by spin-coating of the PSS solution in THF organic solvent onto Si-wafer substrates and curing. The electron trapping of the PSS thin films was confirmed by the capacitance-voltage (C-V) measurements performed within the metal-insulator-semiconductor (MIS) device structure. And the quantum well electronic structure of the PSS thin film, which was thought to be the origin of the electron trapping, was investigated by a combination of theoretical and experimental methods: density functional theory (DFT) calculations in Gaussian03 package and spectroscopic techniques such as near edge X-ray absorption fine structure spectroscopy (NEXAFS) and photoemission spectroscopy (PES). The electron trapping properties of the PSS thin film of quantum well structure are closely related to intra- and inter-polymer chain electron transports. Among them, the intra-chain electron transport was theoretically studied using the Atomistix Toolkit (ATK) software based on the non-equilibrium Green's function (NEGF) method in conjunction with the DFT.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.2410-2412
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• 2005

In this study, two types of PS substrate were fabricated for sensing of chemical and biological substances. For sensing of the humidity and chemical analyzes such as $CH_3OH$ or $C_2H_5OH$, PS layers are prepared by photoelectrochemical etching of silicon wafer in aqueous hydrofluoric acid solution. To evaluate their sensitivity, we measured the resistance variation of the PS diaphragm. As the amplitude of applied voltage increases from 2 to 6Vpp at constant frequency of 5kHz, the resistance variation for humidity sensor rises from 376.3 to $784.8{\Omega}$/%RH. And the sensitivities for $CH_3OH$ and $C_2H_5OH$ were 0.068 uA/% and 0.212 uA/%, respectively. For biological sensing application, amperometric urea sensors were fabricated based on porous silicon(PS), and planar silicon(PLS) electrode substrates by the electrochemical methods. Pt thin film was sputtered on these substrates which were previously formed by electrochemical anodization. Poly (3-methylthiophene) (P3MT) were used for electron transfer matrix between urease(Urs) and the electrode phase, and Urs also was by electrochemically immobilized. Effective working area of these electrodes was determined for the first time by using $Fe(CN)_6^{3-}/Fe(CN)_6^{4-}$ redox couple in which nearly reversible cyclic voltammograms were obtained. The $i_p$ vs $v^{1/2}$ plots show that effective working electrode area of the PS-based Pt thin film electrode was 1.6 times larger than the PLS-based one and we can readily expect the enlarged surface area of PS electrode would result in increased sensitivity by ca. 1.6 times. Actually, amperometric sensitivity of the Urs/P3MT/Pt/PS electrode was ca 0.91uA/$mM{\cdot}cm^2$, and that of the Urs/P3MT/Pt/PLS electrode was ca. 0.91uA/$mM{\cdot}cm^2$ in a linear range of 1mmol/L to 100mmol/L urea concentrations

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.456-456
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• 2009

Boron doping on an n-type Si wafer is requisite process for IBC (Interdigitated Back Contact) solar cells. Fiber laser annealing is one of boron doping methods. For the boron doping, uniformly coated or deposited film is highly required. Plasma enhanced chemical vapor deposition (PECVD) method provides a uniform dopant film or layer which can facilitate doping. Because amorphous silicon layer absorption range for the wavelength of fiber laser does not match well for the direct annealing. In this study, to enhance thermal affection on the existing p-a-Si:H layer, a ${\mu}c$-Si:H intrinsic layer was deposited on the p-a-Si:H layer additionally by PECVD. To improve heat transfer rate to the amorphous silicon layer, and as heating both sides and protecting boron eliminating from the amorphous silicon layer. For p-a-Si:H layer with the ratio of $SiH_4$ : $B_2H_6$ : $H_2$ = 30 : 30 : 120, at $200^{\circ}C$, 50 W, 0.2 Torr for 30 minutes, and for ${\mu}c$-Si:H intrinsic layer, $SiH_4$ : $H_2$ = 10 : 300, at $200^{\circ}C$, 30 W, 0.5 Torr for 60 minutes, 2 cm $\times$ 2 cm size wafers were used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the laser condition set of 20 ~ 27 % of power, 150 ~ 160 kHz, 20 ~ 50 mm/s of marking speed, and $10\;{\sim}\;50 {\mu}m$ spacing with continuous wave mode of scanner lens showed the correlation between lifetime and sheet resistance as $100\;{\Omega}/sq$ and $11.8\;{\mu}s$ vs. $17\;{\Omega}/sq$ and $8.2\;{\mu}s$. Comparing to the singly deposited p-a-Si:H layer case, the additional ${\mu}c$-Si:H layer for doping resulted in no trade-offs, but showed slight improvement of both lifetime and sheet resistance, however sheet resistance might be confined by the additional intrinsic layer. This might come from the ineffective crystallization of amorphous silicon layer. For the additional layer case, lifetime and sheet resistance were measured as $84.8\;{\Omega}/sq$ and $11.09\;{\mu}s$ vs. $79.8\;{\Omega}/sq$ and $11.93\;{\mu}s$. The co-existence of $n^+$layeronthesamesurfaceandeliminating the laser damage should be taken into account for an IBC solar cell structure. Heavily doped uniform boron layer by fiber laser brings not only basic and essential conditions for the beginning step of IBC solar cell fabrication processes, but also the controllable doping concentration and depth that can be established according to the deposition conditions of layers.