• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.10
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• pp.68-76
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• 1997

In this paper, design parameters of rapid thermal processing(RTP) to minimize the wafer temperature uniformity errors are proposed. Lamp ring positions and the wafer height are important parameters for wafer temperature uniformity in RTP. We propose the method to seek lamp ring positions and the wafer gheight for optimal temperature uniformity. The proposed method is applied to seek optimal lamp ring positions and the wafer feight of 8 inch wafer. To seek the optimal lamp ring positions and the wafer height, we vary lamp ring positions and the wafer height and then formulate the wafer temperature uniformity problem to the linear programming problem. Finally, it is shown that the wafer temperature uniformity in RTP designed by optimal problem. Finally, it is hsown that the wafer temperature uniformity is RTP designed by optimal parameters is improved to comparing with RTP designed by the other method.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.32 no.2
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• pp.149-157
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• 2008

During CVD process of semiconductor wafer fabrication, maintaining the uniformity of temperature distribution at wafer top surface is one of the key factors affecting the quality of final products. Effect of contact conductance between wafer and hot plate on predicted temperature of wafer was investigated. The validity of opaque wafer assumption was also examined by comparing the predicted results with Discrete Ordinate solutions accounting for semitransparent radiative characteristics of silicon. As the contact conductance increases predicted wafer temperature increases and the differences between maximum and minimum temperatures within wafer and between wafer and hot plate top surface temperatures decrease. The opaque assumption always overpredicted the wafer temperature compared to semitransparent calculation. The influences of surrounding reactor inner wall temperature and hot plate configuration are then discussed.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1508-1511
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• 1997

In this paper, design parameters of Rapid Thermal Processing(RrW) to minimize the wafer tempera ture uniformity errors are proposed. 1,anip ling positions and the wafer height are important parameters for waf er temperature uniformity in R'I'P. We propose the method to seek lamp ling positions and the wafer height for optimal temperature uniformity. l'he ~~roposed method is applied to seek optimal lamp ling positions and the waf er height of 8 inch wafer. 'I'o seek the optimal lamp ling positions and the wafer height, we var\ulcorner. lamp ling 110s itions and the wafer height and then formulate the wafer temperature uniformity problem to the linear programmi ng problem. Finally, it is shown that the wafer temperature uniformity in RI'I' designed by optimal prarneters is improved to comparing with Ii'l'P designed by the other method.

• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.39-44
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• 2013

In the semiconductor heat-treatment process, the temperature uniformity determines the film quality of a wafer. This film quality effects on the overall yield rate. The heat transfer of the wafer surface in the heat-treatment process equipment is occurred by convection and radiation complexly. Because of this, there is the nonlinearity between the wafer temperature and reactor. Therefore, the accurate prediction of temperature on the wafer surface is difficult without the direct measurement. The thermal camera and the T/C wafer are general ways to confirm the temperature uniformity on the heat-treatment process. As above ways have limit to measure the temperature in the precise domain under the micro-scale. In this study, we developed the thin film type temperature sensor using the MEMS technology to establish the system which can measure the temperature under the micro-scale. We combined the experiment and numerical analysis to verify and calibrate the system. Finally, we measured the temperature on the wafer surface on the semiconductor process using the developed system, and confirmed the temperature variation by comparison with the commercial T/C wafer.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.81-87
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• 1994

We used IR laser inteferometric technique for measuring the temperature of wafer during cryogenic ECR etching. Using this technique, the effect of RF bias power and microwave power on the wafer temperature during etching period is investigated. As the RF bias power and microwave power was increased, the temperature of the wafer considerably increased and we concluded that to prevent the increase of substrate temperature during etching period, an adequate wafer cooling is needed.

• Journal of the Korean Society of Visualization
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• v.13 no.3
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• pp.24-28
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• 2015

The temperature of the wafer batch in the furnace was calculated and its visualized temperature field was analyzed. The main heat transfer mechanisms from the heater wall to the wafers were radiation and conduction, and the finite difference method was used to analyze the complex heat transfer including those two mechanisms. The visualized temperature field shows that the direction of the heat flux in the wafer batch varies during the heating process, and the heat in the wafer batch diffuses faster by conduction within the wafer than by radiation between the wafers, in the condition of the constant temperature at the heater wall and cap.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.1-7
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• 2017

Multi-wafer planetary type chemical vapor deposition reactors are widely used in thin film growth and suitable for large scale production because of the high degree of growth rate uniformity and process reproducibility. In this study, a two-dimensional model for estimating the effect of the gap between satellite and wafer on the wafer surface temperature distribution is developed and analyzed using computational fluid dynamics technique. The simulation results are compared with the results obtained from an analytical method. The simulation results show that a drop in the temperature is noticed in the center of the wafer, the temperature difference between the center and wafer edges is about $5{\sim}7^{\circ}C$ for all different ranges of the gap, and the temperature of the wafer surface decreases when the size of the gap increases. The simulation results show a good agreement with the analytical ones which is based on one-dimensional heat conduction model.

• Proceedings of the KSME Conference
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• 2000.11b
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• pp.261-266
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• 2000

Temperature variation during silicon wafer baking is mainly due to natural convection caused by temperature difference between silicon wafer and upper plate. Several cases are tested and calculated numerically to improve temperature uniformity. The temperature difference and velocity magnitude in the flow cell is reduced for a small gap between the wafer and upper plate because the natural convection force is suppressed in the small space. The uniform temperature distribution can be obtained with controling the incoming flow distribution from the upper plate. An alternative method is the adiabatic wall condition on the upper plate to maintain the temperature uniformity within $0.3^{\circ}C$ on the water plate.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.647-653
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• 1988

A rapid thermal annealing system using tungsten halogen lamp has been designed and assembled. A control scheme where the temperature control is executed with calculated wafer temperature by considering the thermocouple delay rather than measured thermocouple temperature,is proposed. This control scheme gives more accurate control of the wafer temperature. In addition, the distribution of transmitted light power to the wafer in the system has been simulated, and lamp interval modification has been able to give more uniform light power distribution. Considering incident light spectrum, absorption, reflection, radiation of silicon, etc., temperature profile has been simulated. When the light power uniformity on the 3" wafer is below 1%, the temperature uniformity is about 2%.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.19-24
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• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.