• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.2
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• pp.185-193
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• 1996

$2.5^{\circ}\;and\;5^{\circ}$ tilted (100) Si wafer were oxidized in dry oxygen, and the differences in thermal oxidation behavior and oxidation induced stacking faults (OSF) between specimens were investigated. Ellipsometer measurements of the oxide thickness produced by oxidation in dry oxygen from 900 to $1200^{\circ}C$ showed that the oxidation rates of the tilted (100) Si were more rapid than those of the (100) Si and the differences between them decreased as the oxidation temperature increased. The activation energies based on the parabolic rate constant, B for (100) Si, $2.5^{\circ}$ off (100) Si and $5^{\circ}$ off (100) Si were 27.3, 25.9, 27.6 kcal/mol and those on the linear rate constant, B/A were 58.6, 56.6, 57.6 kcal/mol, respectively. Also, considerable decrease in the density of oxidation induced stacking faults for the $5^{\circ}$ off (100) Si was observed through optical microscopy after preferentially etching off the oxide layer, and the angle of stacking faults were changed with tilted angles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.479-480
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.603-604
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• 2009

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.7-13
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• 2013

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.1 no.1
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• pp.66-73
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• 1991

During the growth of macroscopically dislocation-free Czochralski silicon crystal, micro precipitates causing stacking faults in the silicon wafer during the oxidation are formed Thermal history the cryscausing acquire during the growth process is known to be a key factor determining the nucleation of this micro precipitates. In this article, various mechanisms suggested on the formation of microdefects in the silicon crystal are reviewed to secure the nucleation mechanism of the micro precipitates causing OSF whose pattern is normally ring or annular in CZ silicon crytal. B-defects which are known as vacancy clustering are considered to be the heterogeneous nucleation sites for the micro precipitates causing OSF in the CZ silicon crystals.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.223.1-223.1
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• 2013

Since sapphire single crystal is one of the materials that have excellent mechanical and optical properties, the single crystal is widely used in various fields, and the demand for the use of substrate of LED devices is increasing rapidly. However, crystal defects such as dislocations and stacking faults worsen the properties of the single crystal intensely. When sapphire wafer of single crystal is used as LED substrate, especially, crystal defects have a strong influence on the characteristics of a film deposited on the wafer. In such a case quantitative assessment of the defects is essential, and the evaluation technique is now becoming one of the most important factors in commercialization of sapphire wafer. Wet etching is comparatively easy and accurate method to estimate dislocation density of single crystal because etching reaction primarily takes place where dislocations reached crystal surface which are chemically weak points, and produces etch pit. In the present study, the formation behavior of etch pits and etching time dependence were studied systematically. Etch pit density(EPD) analysis using optical microscope was also conducted and measurement uncertainty of EPD was studied to confirm the reliability of the results. EPDs and measurement uncertainties for 4 inch sapphire wafers were analyzed in terms of 5 and 21 points EPD readings. EPDs and measurement uncertainties in terms of 5 points readings for 4 inch wafers were compared by 2 organizations. We found that the average EPD value in terms of 5 points readings for a 4 inch sapphire wafer may represent the EPD value of the wafer.

• Proceedings of the KWS Conference
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• 2006.10a
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• pp.190-192
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• 2006

The 3-dimensional(3D) chip stacking technology is one of the leading technologies to realize a high density and high performance system in package(SIP). It could be found that it is the advanced process of through-hole via formation with the minimum damaged on the Si-wafer. Laser ablation is very effective method to penetrate through hole on the Si-wafer because it has the advantage that formed under $100{\mu}m$ diameter through-hole via without using a mask. In this paper, we studied the optimum method for a formation of through-hole via using femto-second laser heat sources. Furthermore, the processing parameters of the specimens were several conditions such as power of output, pulse repetition rate as well as irradiation method and time. And also the through-hole via form could be investigated and analyzed by microscope and analyzer.