• 한국결정성장학회지
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• 제6권2호
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• pp.185-193
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• 1996

(100) Si wafer를 $2.5^{\circ},\;5^{\circ}$ 기울인 뒤, dry $O_{2}$ 분위기에서 산화시킴으로써, 시편들 간의 산화 거동 및 산화에 의한 적층 결함 특성의 차이를 알아보았다. 시편을 $900~1200^{\circ}C$에서 산화시키고 ellipsometer로 두께를 측정한 결과 저탈각 (100) Si이 (100) Si보다 산화 속도가 빨랐으며, $5^{\circ}$ off면이 $2.5^{\circ}$ off면보다 더 빨랐다. 결정방향에 따른 산화속도 차이는 산화 온도가 높아질수록 줄어들었다. 각 시편의 속도 상수에 대한 활성화 에너지는 포물 성장 속도 상수의 경우 (100) Si, $2.5^{\circ}$ off (100) Si, $5^{\circ}$ off Si이 각각 27.3, 25.9, 27.6 kcal/mol이였고, 선형 성장 속도 상수는 58.6, 56.6, 57.4 kcal/mol이였다. 또한, 두 시편에 대해 산화막을 선택 식각하 고 광학 현미경으로 관찰하여, (100) Si에 비해 $5^{\circ}$ off된 면의 산화에 의한 적층 결함 밀도가 훨씬 낮음을 확인하였고, 적층 결함 간의 각도가 달라짐을 확인하였다.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.479-480
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• 2012

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 추계학술대회 논문집
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• pp.603-604
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• 2009

• 마이크로전자및패키징학회지
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• 제19권4호
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• pp.71-78
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• 2012

본 논문은 기존의 미세화 경향에 대한 bumpless through-silicon via (TSV)를 적용한 웨이퍼 레벨3차원 적층기술과 그 장점에 대해 소개한다. 3차원 적층을 위한 박막화 공정, 본딩 공정, TSV 공정별로 문제점과 그 해결책에 대해 자세히 설명하며, 특히 $10{\mu}m$ 이하로 박막화한 로직 디바이스의 특성 변화에 대한 결과를 보고한다. 웨이퍼 박막화 공정에서는 기계적 강도 변동 요인, 금속 불순물에 대한 gettering 대책에 대해 논의되며, 본딩 공정에서는 웨이퍼의 두께 균일도를 높이기 위한 방법에 대해 설명한다. TSV형성 공정에서는 누설 전류 발생 원인과 개선 방법을 소개한다. 마지막으로 본 기술을 적용한 3차원 디바이스에 대한 roadmap에 관해 논의할 것이다.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• 마이크로전자및패키징학회지
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• 제20권1호
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• pp.7-13
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• 2013

3D 적층 IC 개발을 위한 본딩 기술의 현황에 대해 알아보았다. 실리콘 웨이퍼를 본딩하여 적층한 후 배선 공정을 진행하는 wafer direct bonding 기술보다는 배선 및 금속 범프를 먼저 형성한 후 금속 본딩을 통해 웨이퍼를 적층하는 공정이 주로 연구되고 있다. 일반적인 Cu 열압착 본딩 방식은 높은 온도와 압력을 필요로 하기 때문에 공정온도와 압력을 낮추기 위한 연구가 많이 진행되고 있으며, 그 가운데서 Ar 빔을 조사하여 표면을 활성화 시키는 SAB 방식과 실리콘 산화층과 Cu를 동시에 본딩하는 DBI 방식이 큰 주목을 받고 있다. 국내에서는 Cu 열압착 방식을 이용한 웨이퍼 레벨 적층 기술이 현재 개발 중에 있다.

• 한국결정성장학회지
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• 제1권1호
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• pp.66-73
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• 1991

During the growth of macroscopically dislocation-free Czochralski silicon crystal, micro precipitates causing stacking faults in the silicon wafer during the oxidation are formed Thermal history the cryscausing acquire during the growth process is known to be a key factor determining the nucleation of this micro precipitates. In this article, various mechanisms suggested on the formation of microdefects in the silicon crystal are reviewed to secure the nucleation mechanism of the micro precipitates causing OSF whose pattern is normally ring or annular in CZ silicon crytal. B-defects which are known as vacancy clustering are considered to be the heterogeneous nucleation sites for the micro precipitates causing OSF in the CZ silicon crystals.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.223.1-223.1
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• 2013

Since sapphire single crystal is one of the materials that have excellent mechanical and optical properties, the single crystal is widely used in various fields, and the demand for the use of substrate of LED devices is increasing rapidly. However, crystal defects such as dislocations and stacking faults worsen the properties of the single crystal intensely. When sapphire wafer of single crystal is used as LED substrate, especially, crystal defects have a strong influence on the characteristics of a film deposited on the wafer. In such a case quantitative assessment of the defects is essential, and the evaluation technique is now becoming one of the most important factors in commercialization of sapphire wafer. Wet etching is comparatively easy and accurate method to estimate dislocation density of single crystal because etching reaction primarily takes place where dislocations reached crystal surface which are chemically weak points, and produces etch pit. In the present study, the formation behavior of etch pits and etching time dependence were studied systematically. Etch pit density(EPD) analysis using optical microscope was also conducted and measurement uncertainty of EPD was studied to confirm the reliability of the results. EPDs and measurement uncertainties for 4 inch sapphire wafers were analyzed in terms of 5 and 21 points EPD readings. EPDs and measurement uncertainties in terms of 5 points readings for 4 inch wafers were compared by 2 organizations. We found that the average EPD value in terms of 5 points readings for a 4 inch sapphire wafer may represent the EPD value of the wafer.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년 추계학술발표대회 개요집
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• pp.190-192
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• 2006

The 3-dimensional(3D) chip stacking technology is one of the leading technologies to realize a high density and high performance system in package(SIP). It could be found that it is the advanced process of through-hole via formation with the minimum damaged on the Si-wafer. Laser ablation is very effective method to penetrate through hole on the Si-wafer because it has the advantage that formed under $100{\mu}m$ diameter through-hole via without using a mask. In this paper, we studied the optimum method for a formation of through-hole via using femto-second laser heat sources. Furthermore, the processing parameters of the specimens were several conditions such as power of output, pulse repetition rate as well as irradiation method and time. And also the through-hole via form could be investigated and analyzed by microscope and analyzer.