• 한국정보처리학회논문지
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• 제7권1호
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• pp.115-125
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• 2000

본 논문에서는 반도체 웨이퍼 세정 장비를 위한 모니터링 시스템의 기본 요소와 이를 기반으로 모니터링 시스템 모델을 제시한다. 기본 요소는 모니터링 시스템에서 요구되는 필수적인 기능으로써 제어 시스템과의 통신, 사용자 인터페이스, 원격 감시 시스템과의 통신, 감시 데이터 관리, 테스크간 통신으로 구성된다. 기본 요소들의 기능과 기본 요소들 간의 관계를 정의하여 독립된 테스크로 설계한다. 제시한 모델의 타당성을 평가하기 위하여 Windows NT에서 Visual C++를 사용하여 기본 요소들을 구현하여 반도체 웨이퍼 세정 장비의 모니터링 시스템에 적용해 보았다.

• Journal of Welding and Joining
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• 제26권1호
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• pp.12-16
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• 2008

본 보고에서는 3D 패키징에서 중요한 공정의 하나인 초박막 Si 웨이퍼 Thinning 공정에 대해 간략히 소개하였고, 표면처리에 대해 살펴보았다. 기계적, 특히 전기적 Damage를 줄이기 위한 최적화된 Thinning 공정과 신뢰성 분석 및 평가, 그리고 초박막 웨이퍼 핸들링 방법 등이 시스템적으로 개발되는 것이 중요하다. 칩 소형화 추세와 더불어 3D 패키징 기술이 중요시되는 산업 요구에 맞추어 향후 웨이퍼 Thinning 기술을 포함한 3D 기술의 핵심 공정기술들은 그 중요성이 증대할 것이고, 이에 대한 활발한 연구가 진행되리라 기대한다.

• 제어로봇시스템학회논문지
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• 제6권6호
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• pp.500-505
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• 2000

This paper deals with wafer temperature uniformity control essential in rapid thermal processing (RTP). One of the important control objectives of RTP is to keep the temperature over the wafer surface as uniformly as possible. For this, a discrete time state equation around the operating point is first identified by using the subspace fitting method, and a multivariable LQG(Linear Quadratic Gaussian) controller is designed based on the identified model. Simulation and experimental results show improvement in temperature uniformity over the conventional PID method.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2001년도 춘계학술대회 발표논문집
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• pp.79-81
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• 2001

저압 기상 영역에서 Anhydrous HF 가스와 Methanol vapor를 사용하는 산화막 식각공정을 수행하기 위하여 (1) 반응기 부피의 최소화, (B) 공정압력의 최소화, (3) 고순도 알루미나 Reactor 적용, (4) Cluster화의 개념을 적용한 VPC 장치를 제작하였다. Wafer의 온도, HF의 분압 및 Working Pressure 등의 공정변수에 따른 Oxide Wafer의 식각특성의 변화를 확인하였다. 또한 Etch Uniformity를 향상시키기 위하여 Shower Head 구조를 변경시켜서 실험하였으며, CFD Simulation을 이용하여 Reactor내에서의 HF gas 및 Methanol vapor의 분율을 예측하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.433-433
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• 2012

As the requirement in patterning geometry continuously shrinks down, the termination of etch process at the exact time became crucial for the success in nano patterning technology. By virtue of real-time optical emission spectroscopy (OES), etch end point detection (EPD) technique continuously develops; however, it also faced with difficulty in low open ratio etching, typically in self aligned contact (SAC) and one cylinder contact (OCS), because of very small amount of optical emission from by-product gas species in the bulk plasma glow discharge. In developing etching process, one may observe that coupon test is being performed. It consumes costs and time for preparing the patterned sample wafers every test in priority, so the coupon wafer test instead of the whole patterned wafer is beneficial for testing and developing etch process condition. We also can observe that etch open area is varied with the number of coupons on a dummy wafer. However, this can be a misleading in OES study. If the coupon wafer test are monitored using OES, we can conjecture the endpoint by experienced method, but considering by data, the materials for residual area by being etched open area are needed to consider. In this research, we compare and analysis the OES data for coupon wafer test results for monitoring about the conditions that the areas except the patterns on the coupon wafers for real-time process monitoring. In this research, we compared two cases, first one is etching the coupon wafers attached on the carrier wafer that is covered by the photoresist, and other case is etching the coupon wafers on the chuck. For comparing the emission intensity, we chose the four chemical species (SiF2, N2, CO, CN), and for comparing the etched profile, measured by scanning electron microscope (SEM). In addition, we adopted the Dynamic Time Warping (DTW) algorithm for analyzing the chose OES data patterns, and analysis the covariance and coefficient for statistical method. After the result, coupon wafers are over-etched for without carrier wafer groups, while with carrier wafer groups are under-etched. And the CN emission intensity has significant difference compare with OES raw data. Based on these results, it necessary to reasonable analysis of the OES data to adopt the pre-data processing and algorithms, and the result will influence the reliability for relation of coupon wafer test and whole wafer test.

• 한국기계가공학회지
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• 제11권1호
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• pp.1-6
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• 2012

The polishing of silicon wafers has an important role in semiconductor manufacturing. Generally, getting a flat surface such as a mirror is the purpose of the process. The wafer surface roughness is affected by many variables such as the characteristics of the carrier head unit, operation, speed, the pad and slurry temperature. Optimum process conditions for experimental temperature, pH value, down-force, slurry ratio are investigated, time is used as a fixed factor. This study carried out a series of experiments at varying platen, chuck rpm and oscillation cpm taking particular note of the difference between the rpm and the affect it has on the surface roughness. In this experiment determine the optimum conditions for polishing silicone wafers.

• 한국정밀공학회지
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• 제20권12호
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• pp.105-114
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• 2003

In this study, a dicing machine with vision system was built and an algorithm for automatic alignment was developed for dual camera system. The system had a macro and a micro inspection tool. The algorithm was formulated from geometric relations. When a wafer was put on the cutting stage within certain range, it was inspected by vision system and compared with a standard pattern. The difference between the patterns was analyzed and evaluated. Then, the stage was moved by x, y, $\theta$ axes to compensate these differences. The amount of compensation was calculated from the result of the vision inspection through the automatic alignment algorithm. The stage was moved to the compensated position and was inspected by vision for checking its result again. Accuracy and validity of the algorithm was discussed from these data.

• 반도체디스플레이기술학회지
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• 제2권1호
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• pp.15-19
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• 2003

Spin etcher can process frontside and backside on the wafer, which is used for etching, stripping, cleaning and wafer reclamation. A new generation of spin etchers has been designed to meet 300mm wafer processing. The larger header and higher spin speed make vibration problem a severe problem in developing equipments. This study shows schematic process of solving practical vibration problems, where it is required to analyze the principal ca uses of vibration problem and find out the method of vibration reduction in spin etcher. The vibration under normal operation is measured in time domain and is analyzed in frequency domain. And modal parameters are obtained through modal test. Using the modal parameters from experiments, the model of finite element method is formulated. From diagnosis using many measurements and analyses, it can be shown that main cause of vibration is unbalance of head.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회B
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• pp.2369-2374
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• 2008

In the precision hot plate for wafer processing, the temperature uniformity of upper plate surface is one of the key factors affecting the quality of wafers. Precision hot plates require temperature variations less than ${\pm}1.5%$ during heating to $120^{\circ}C$. In this study, we have manufactured the flat plate heat pipe hot chuck of circle type(300mm) and investigated the operating characteristics of flat plate heat pipe hot chuck experimentally. Various liquids(aceton, FC-40, water) were used as the working fluid and charging ratio was changed($14{\sim}36\;vol.%$). Several cases were tested to improve temperature uniformity. Major working fluid to be investigated was water. Using water, various parameters such as charging ratio, wafer operation on-off time, different working fluids. In case of water, the temperature uniformity was ${\pm}1.5%$, response time of wafer were investigated.

• 한국산학기술학회논문지
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• 제17권6호
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• pp.708-714
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• 2016

오늘날 반도체 분야의 산업에서는 데이터 처리 속도가 빠르고 대용량 데이터 처리 수행 능력을 갖는 반도체 기술 개발이 활발히 진행 되고 있다. 반도체 제작에서 패키징 공정은 칩을 외부 환경으로부터 보호 하고 접속 단자 간 전력을 공급하기 위해 진행하는 공정이다. 근래에는 생산성이 높은 웨이퍼 레벨 패키지 공정이 주로 사용되고 있다. 웨이퍼 레벨 패키지 공정에서 웨이퍼 상의 모든 실리콘 다이는 몰딩 공정 중에 높은 몰딩 압력과 고온의 열 영향을 받는다. 실리콘 다이에 작용하는 몰딩 압력 및 열 영향은 다이 시프트 및 웨이퍼 휨 현상을 초래하며, 이러한 다이 시프트 및 웨이퍼 휨 현상은 후속 공정으로 칩 하부에 구리 배선 제작을 하는데 있어 배선 위치 정밀도의 문제를 발생시킨다. 따라서 본 연구에서는 다이 시프트 최소화를 위한 공정 개발을 목적 으로 다이 시프트 측정 데이터를 수집하기 위해 다이 시프트 비전 검사 장비를 구축하였다.