• Journal of ILASS-Korea
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• v.12 no.4
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• pp.185-190
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• 2007

There is a growing interest to develop a new cleaning technology to overcome the disadvantages of wet cleaning technologies such as environmental pollution and the cleaning difficulty of contaminants on integrated circuits. Laser cleaning is a potential technology to remove various pollutants on a wafer surface. However, there is no fundamental data about cleaning efficiencies and cleaning mechanisms of contaminants on a wafer surface using a laser cleaning technology. Therefore, the cleaning characteristics of a wafer surface using an excimer laser were investigated in this study. Fingerprint consisting of inorganic and organic materials was chosen as a representative of pollutants and the effectiveness of a laser irradiation on a wafer cleaning has been investigated qualitatively and quantitatively. The results have shown that cleaning degree is proportional to the laser irradiation time and repetition rate, and quantitative analysis conducted by an image processing method also have shown the same trend. Furthermore, the cleaning efficiency of a wafer contaminated by fingerprint strongly depended on a photothermal cleaning mechanism and the species were removed in order of hydrophilic and hydrophobic contaminants by laser irradiation.

• Transactions of Materials Processing
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• v.13 no.3
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• pp.225-229
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• 2004

Chemical Mechanical Polishing(CMP) process becomes one of the most important semiconductor processes. But the basic mechanism of CMP still does not established. Slurry fluid dynamics that there is a slurry film between a wafer and a pad and contact mechanics that a wafer and a pad contact directly are the two main studies for CMP. This paper based on the latter one, especially on the abrasion wear model. Material Removal Rate(MRR) is calculated using the trajectory length of every point on a wafer during the process time. Both the rotational velocity of a wafer and a pad and the wafer oscillation velocity which has omitted in other studies are considered. For the purpose of the verification of our simulation, we used the experimental results of S.H.Li et al. The simulation results show that the tendency of the calculated MRR using the relative velocity is very similar to the experimental results and that the oscillation effect on MRR at a real CMP condition is lower than 1.5%, which is higher than the relative velocity effect of wafer, and that the velocity factor. not the velocity itself, should be taken into consideration in the CMP wear model.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.632-641
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• 2011

This paper presents a position error recognition system when the wafer is mounted in cleaning equipment among the wafer manufacturing processes. The proposed system is to enhance the performance in cost and reliability by preventing the wafer cleaning system from damaging by alerting it when it is put in correct position. The proposed algorithm is in obtaining a mapping function from camera and physical wafer by designing and manufacturing the radial shape calibrator to reduce the error by using the conventional chess board one. The system is to install in-line process using high reliable and high accurate position recognition. The experimental results show that the performance of the proposed system is better than that of the existing method for detecting errors within tolerance.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.419-420
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• 2009

• Proceedings of the Korean Society of Laser Processing Conference
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• 2003.05a
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• pp.107-110
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• 2003

• Proceedings of the Korean Society of Laser Processing Conference
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• 2005.06a
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• pp.15-20
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• 2005

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.251-256
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• 2004

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.125-134
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• 2006

Process & mechanism $\blacklozenge$ The process consists from two steps which are laser processing step and separation steop. $\blacklozenge$ The wavelength of laser beam is transmissible wavelength for the wafer. However, inside of Si wafer is processed due to temperature dependence of optical absorption coefficient Advantage & Application $\blacklozenge$ Advantages are high speed dicing, no debris contaminants, completely dry process, etc. $\blacklozenge$ The cutting edges were fine, The lifetime and endurances did not degrade the device characteristics $\blacklozenge$ A separation of a wafer with DAF was introduced as an application for SiP

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.