• Journal of the Korean Society for Precision Engineering
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• v.17 no.5
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• pp.70-75
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• 2000

After the patterning and probe process of wafer have been achieved, the dicing process is necessary to separate chips from a wafer. The dicing process cuts a wafer to lengthwise and crosswise direction to make many chips by using narrow circular rotating diamond blade. But inferior goods are made under the influence of complex dicing environment such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using feature extraction in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, two features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision. a threshold method is adopted to classify the dicing process into normal and abnormal dicing. Experiment have been performed for GaAs semiconductor wafer. Based upon observation of the experimental results, the proposed scheme shown a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 12.8%.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.47-49
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• 2006

Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.4 s.247
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• pp.306-313
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• 2006

Automated material handling system is being used as a method to reduce manufacturing cost in the semiconductor and flat panel displays (FPDs) manufacturing process. Those are considering switch-over from the traditional cassette system to single-substrate transfer system to reduce raw materials of stocks in the processing line. In the present study, the wafer transportation speed has been evaluated by numerical and experimental method for three propulsion nozzle array (face, front, rear) in an air levitation system. Test facility for 300 mm wafer was equipped with two control tracks and a transfer track of 1,500mm length. The diameter of propulsion nozzle is 0.8mm and air velocity of wafer propulsion is $50\sim150m/s$. We found that the experimental results of the wafer transportation speed were well agreed with the numerical ones. Namely, the predicted values of the maximum wafer transportation speed are higher than those values of experimental data by 16% and the numerical result of the mean wafer transportation speed is higher than the experimental result within 20%.

• Korean Journal of Computational Design and Engineering
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• v.19 no.3
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• pp.214-223
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• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.06a
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• pp.161-166
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• 2003

Semiconductor Manufacturing has emerged as one of the most Important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer

• Journal of Digital Convergence
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• v.15 no.9
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• pp.211-221
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• 2017

The semiconductor industry develops and maintains software embedded in computer-controlled tools and facilities, to process and manufacture high-tech products. Upgrading embedded softwares for semiconductor processing robots and machinery is one of the basic activities that must be performed in order to maintain product quality and integrity. Maintenance and enhancement of embedded software consume a major portion of the total life cycle cost of a system. However, the area has been given little attention in the literature. 502 maintenance and enhancement cases, related to embedded softwares in wafer processing machines, were selected at random for analysis. Practical implications are also discussed.

• Journal of the Optical Society of Korea
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• v.10 no.3
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• pp.124-129
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• 2006

We have developed a compact and cost-effective camera module on the basis of wafer-scale-replica processing. A multiple-layered structure of several aspheric lenses in a mobile-phone camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. This wafer-scale processing leads to at least 95% yield in mass-production, and potentially to a very slim phone with camera-module less than 2 mm in thickness. We have demonstrated a VGA camera module fabricated by the wafer-scale-replica processing with various UV-curable polymers having refractive indices between 1.4 and 1.6, and with three different glass-wafers of which both surfaces are embossed as aspheric lenses having $230{\mu}m$ sag-height and aspheric-coefficients of lens polynomials up to tenth-order. We have found that precise compensation in material shrinkage of the polymer materials is one of the most technical challenges, in orderto achieve a higher resolution in wafer-scaled lenses for mobile-phone camera modules.

• Composites Research
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• v.20 no.5
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• pp.49-55
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• 2007

Nanocomposite blade for dicing semiconductor wafer is investigated for micro/nano-device and micro/nano-fabrication. While metal blade has been used for dicing of silicon wafer, polymer composite blades are used for machining of quartz wafer in semiconductor and cellular phone industry in these days. Organic-inorganic material selection is important to provide the blade with machinability, electrical conductivity, strength, ductility and wear resistance. Maintaining constant thickness with micro-dimension during shaping is one of the important technologies fer machining micro/nano fabrication. In this study the fabrication of blade by wet processing of mixing conducting nano ceramic powder, abrasive powder phenol resin and polyimide has been investigated using an experimental approach in which the thickness differential as the primary design criterion. The effect of drying conduction and post pressure are investigated. As a result wet processing techniques reveal that reliable results are achievable with improved dimension tolerance.

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.