• Journal of the Korean Ceramic Society
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• v.49 no.2
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• pp.179-184
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• 2012

The size of various alumina ceramics used in semiconductor and display industry is required to increase with increase in wafer and panel size. In this research, large alumina ceramics were fabricated by uniaxial pressing, cold isostatic pressing and filter pressing with commercial powder and thereafter sintering at $1600^{\circ}C$ in gas furnace. The large alumina ceramics exhibited dense microstructure corresponding to 98.5% of theoretical density and 99.8% of high purity. The impurities and microstructural defects of the alumina were found to influence the resistance and dielectric properties. The volume resistances in these four aluminas were almost the same while the pure alumina was higher value. The dielectric constant, dielectric loss and dielectric strength of aluminas were placed within the range of 10.3~11.5, 0.018~0.036, and 10.1~12.4 kV/mm, respectively.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1825-1828
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• 2008

A simple method for the fabrication of porous nano-master for antireflective surface is presented. In conventional fabrication methods for antireflective surface, coating method with low refractive index has usually been used. However, it is required to have high cost and long times for mass production. In this paper, we suggested the fabrication method of antireflective surface by the hot embossing process using the porous nano patterned master on silicon wafer fabricated by low-temperature anodic aluminum oxidation. Through multi-AAO and etching processes, nano patterned master with high aspect ratio was fabricated at the large area. Pore diameter and inter-pore distance are about 150nm and from 150 to 200nm. In order to replicate anti-reflective structure, hot embossing process was performed by varying the processing parameters such as temperature, pressure and embossing time etc. Finally, antireflective surface can be successfully obtained after etching process to remove selectively silicon layer of AAO master.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.370-373
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.4
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• pp.261-268
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• 1999

Laser-induced thermochemical etching has been recognized as a new powerful method for processing a variety of materials, including metals, semiconductors, ceramics, insulators and polymers. This study presents characteristics of direct etching for Si substrate using focused argon ion laser beam in aqueous KOH and $CCl_2F_2$ gas. In order to determine process conditions, we first theoretically investigated the temperature characteristics induced by a CW laser beam with a gaussian intensity distribution on a silicon surface. Major process parameters are laser beam power, beam scan speed and reaction material. We have achieved a very high etch rate up to $434.7\mum/sec$ and a high aspect ratio of about 6. Potential applications of this laser beam etching include prototyping of micro-structures of MEMS(micro electro mechanical systems), repair of devices, and isolation of opto-electric devices.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.53-57
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• 2006

This paper describes a novel processing technique for fabrication of polymer-derived SiCN (silicone carbonitride) microstructures for super-temperature MEMS applications. PDMS (polydimethylsiloxane) mold is fabricated on SU-8 photoresist using standard UV photolithographic process. Liquid precursor is injected into the PDMS mold. Finally, solid polymer structure is cross-linked using HIP (hot isostatic pressure) at $400^{\circ}C$, 205 bar. Optimum pyrolysis and annealing conditions are determined to form a ceramic microstructure capable of withstanding over $1400^{\circ}C$. The fabricated SiCN ceramic microstructure has excellent characteristics, such as shear strength (15.2 N), insulation resistance ($2.163{\times}10^{14}{\Omega}$) and BDV (min. 1.2 kV) under optimum process condition. These fabricated SiCN ceramic microstructures have greater electric and physical characteristics than bulk Si wafer. The fabricated SiCN microstructures would be applied for supertemperature MEMS applications such as heat exchanger and combustion chamber.

• Transactions of Materials Processing
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• v.13 no.8
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• pp.716-722
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• 2004

Effects of sliding speed, applied load, and thickness of PMMA (Poly Methyl Methacrylate) coating layers on their dry sliding frictional and wear behavior were investigated. Sliding wear tests were carried out using a pin-on-disk wear tester. The PMMA layer was coated on Si wafer by a spin coating process with two different thicknesses, $1.5\mu\textrm{m}$ and $0.8\mu\textrm{m}$. AISI 52100 bearing steel balls were used as a counterpart of the PMMA coating during the wear. Normal applied load and sliding speed were varied. Wear mechanisms of the coatings were investigated by examining worn surfaces using an SEM. Friction coefficient of the coatings decreased with the increase of the applied load. Both adhesion and deformation of the coating determined the coefficient. The thicker PMMA layer with the thickness of $1.5mutextrm{m}$ showed lower friction coefficient than the thinner layer under most test conditions. Effects of sliding speed and applied load on the frictional behavior were varied depending on the thickness of the coating layer.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1497-1499
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• 2000

We give pressure stimulation into organic thin films and then manufacture a device under the accumulation condition that the state surface pressure is 30 [mN/m]. LB layers of Arac. acid deposited by LB method were deposited onto y-type silicon wafer as y-type film. In processing of a device manufacture. we can see the process is good from the change of a surface pressure for organic thin films and transfer ratio of area per molecule. The structure of manufactured device is Au/arachidic acid/Al. the number of accumulated layers are 9$\sim$21. Also. we then examined of the MIM device by means of I-V. The I-V characteristic of the device is measured from -3 to +3[V]. The insulation property of a thin film is better as the distance between electrodes is larger.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.4
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• pp.367-372
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• 2002

The vertically well-aligned carbon nanotubes(CNTs) were successfully grown on Ni coated silicon wafer substrate by DC bias-assisted PECVD(Plasma Enhanced Chemical Vapor Deposition). As a catalyst, Ni thin film of thickness ranging from 15~30nm was prepared by electron beam evaporator method. In order to find the optimum growth condition, the type of gas mixture such as $C_2H_2-NH_3$ was systematically investigated by adjusting the gas mixing ratio at $570^{\circ}C$ under 0.4Torr. The diameter of the grown CNTs was 40~200nm and the diameter of the CNTs increased with increasing the Ni particles size. TEM images clearly showed carbon nanotubes to be multiwalled. The measured turn-on field was $3.9V/\mu\textrm{m}$ and an emission current of $1.4{\times}10^4A/\textrm{cm}^2$ was $7V/\mu\textrm{m}$. The CNTs grown by bias-assisted PECVD was able to demonstrate high quality in terms of vertical alignment, crystallization of graphite and the processing technique at low temperature of $570^{\circ}C$ and this can be applied for the emitter tip of FEDs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.