• 멤브레인
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• 제9권3호
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• pp.185-192
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• 1999

반도체 산업의 wafer 가공공정에서 발생하는 폐수를 재활용하고자 한외여과 공정을 이용한 막분리 공정의 도입 가능성을 검토하였다. Pilot 규모의 장치에 분획분자량이 각각 10,000, 20.000, 30,000인 한외여과막 모듈을 이용하여 투과유속 및 제거율 등을 측정하였다. 투과수의 성상은 SDI15, 탁도, 전기전도도, 실리콘 농도분석을 통해 공정수로 재이용이 가능함을 확인할 수 있었다. 투과유속 저하를 막기 위한 역세척 방법으로는 압축공기와 물은 sweeping 하는 방법이 가장 효과적이었고, 이때 투과유속의 회복율이 높게 나타났다. 분획분자량 30,000인 한외여과막에서 가장 높은 투과유속을 나타내었다. 또한 폐수의 평균 실리콘 입자 평균 함량은 3.8-5.6mg/$\ell$이고, 투과수의 실리콘 입자 함량은 0.2${\mu}g$/$\ell$이하로 나타나 제거율은약 96%이상으로 나타났다.

• 대한기계학회논문집B
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• 제26권4호
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• pp.524-530
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• 2002

Micro electric spark discharge device was fabricated on a FOTURAN glass wafer using MEMS processing technique and its performance of electron discharge and subsequent formation of ignition kernel were tested. Micro electric spark device is an essential subsystem of a power MEMS that has been under development in this laboratories. In a combustion chamber of sub millimeter scale depth, spark electrodes are formed by electroplating Ni on a base plate of FOTURAN glass wafer. Optimization of spark voltage and spark gap is crucial for stable ignition and endurance of the electrodes. Namely, wider spark gaps insures stable ignition but requires higher ignition voltage to overcome the spark barrier. Also, electron discharge across larger voltage tends to erode the electrodes limiting the endurance of the overall system. In the present study, the discharge characteristics of the proptotype ignition device was measured in terms of electric quantities such as voltage and currant with spark gap and end shape as parameters. Discharge voltage shows a little decrease in width of less than 50㎛ and increases with electrode gap size. Reliability test shows no severe damage over 10$\^$6/ times of discharge test resulting in satisfactory performance for application to proposed power MEMS devices.

• 한국재료학회지
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• 제24권8호
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• pp.429-433
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• 2014

As the fabrication technology used in FPDs(flat-panel displays) advances, the size of these panels is increasing and the pattern size is decreasing to the um range. Accordingly, a cleaning process during the FPD fabrication process is becoming more important to prevent yield reductions. The purpose of this study is to develop a FPD cleaning system and a cleaning process using a two-phase flow. The FPD cleaning system consists of two parts, one being a cleaning part which includes a two-phase flow nozzle, and the other being a drying part which includes an air-knife and a halogen lamp. To evaluate the particle removal efficiency by means of two-phase flow cleaning, silica particles $1.5{\mu}m$ in size were contaminated onto a six-inch silicon wafer and a four-inch glass wafer. We conducted cleaning processes under various conditions, i.e., DI water and nitrogen gas at different pressures, using a two-phase-flow nozzle with a gap distance between the nozzle and the substrate. The drying efficiency was also tested using the air-knife with a change in the gap distance between the air-knife and the substrate to remove the DI water which remained on the substrate after the two-phase-flow cleaning process. We obtained high efficiency in terms of particle removal as well as good drying efficiency through the optimized conditions of the two-phase-flow cleaning and air-knife processes.

• Korean Chemical Engineering Research
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• 제53권3호
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• pp.401-406
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• 2015

게터는 반도체와 초소형 전자패키지 소자 내부의 수소와 수증기 같은 기체를 흡착하여 기기 작동 시 방해 기체를 제거하는 기능을 한다. 본 연구에서는 재료와 공정 측면에서 높은 가격 경쟁력을 갖는 게터로, 실리콘 기판에 올라간 다공성 알루미나 구조체를 제조하는 연구를 진행하였다. 기공의 크기가 조절된 양극산화 알루미나(AAO)는 높은 비표면적을 가지며 표면에 OH-기를 다수 포함하므로 높은 효율을 갖는 수분 흡착제로 사용되었다. 등온 수분 흡탈착 곡선으로 분석한 수분 흡착도는 상대습도 35%일 때 2.02%로 우수한 성능을 나타내었다. 즉, 저온에서 사용가능하며, 추가 열원이 필요하지 않아 박막구조의 소형화가 용이하여 내부 손상 및 오염을 방지할 수 있는 게터재를 합성하였다.

• 한국재료학회지
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• 제4권5호
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• pp.510-515
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• 1994

플라즈마 화학 증착법으로 (100)p-type Si wafer위에 $Y_2O_3$-Stabilzed $ZrO_2$박막을 증착하였다. 반응 기체로는 zirconium triflouracethylacetonate[Zr(tfacac) $[Zr(tfacac)_4]$, tri(2.2.6.6 tetramethy1-3, 5-heptanate) yttrium $[Y(DPM)_3]$과 oxygen gas를 사용하였다. X-ray diffraction(XRD)과 fourier Particle induced x-ray emission(PIXE)을 통하여 $Y(DPM)_3$ bubbling temperature가 $160^{\circ}C, 165^{\circ}C, 170^{\circ}C$일때 $Y_2O_3$함량이 12.1mo1%, 20.4mol%, 31.6mol%임을 알 수 있었다. C-V측정에서 $Y(DPM)_3$ bubbling temperature가 증가함에 따라 flat band voltage가 더욱더 음의 방향으로 이동하였다.

• 산업경영시스템학회지
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• 제38권4호
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.

• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.92-97
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• 2021

The importance of processes in cryogenic environments is increasing in a way to address problems such as critical dimension (CD) narrow and bottlenecks in micro-processing. Accordingly, in this paper, we proceed with the design and analysis of Electrostatic Chuck(ESC) and Coolant in cryogenic environments, and present optimal model conditions to provide the temperature distribution analysis of ESC in these environments and the appropriate optimal design. The wafer temperature uniformity was selected as the reference model that the operating conditions of the refrigerant of the liquid nitrogen in the doubled aluminum path were excellent. Design of simulation (DOS) was carried out based on the wheel settings within the selected reference model and the classification of three mass flow and diameter case, respectively. The comparison between factors with p-value less than 0.05 indicates that the optimal design point is when five turns of coolant have a flow rate of 0.3 kg/s and a diameter of 12 mm. ANOVA determines the interactions between the above factor, indicating that mass flow is the most significant among the parameters of interests. In variable selection procedure, Case 2 was also determined to be superior through the two-Sample T-Test of the mean and variance values by dividing five coolant wheels into two (Case 1 : 2+3, Case 2: 3+2). Finally, heat transfer analysis processes such as final difference method (FDM) and heat transfer were also performed to demonstrate the feasibility and adequacy of the analysis process.

• 한국전기전자재료학회논문지
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• 제36권4호
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• pp.332-340
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• 2023

Crystalline silicon solar cells have attracted great attention for their various advantages, such as the availability of raw materials, high-efficiency potential, and well-established processing sequence. Tunnel oxide passivated contact (TOPCon) solar cells are widely regarded as one of the most prospective candidates for the next generation of high-performance solar cells because an efficiency of 26% has been achieved in small-area solar cells. Compared to n-type TOPCon solar cells, the photo conversion efficiency (PCE) of p-type TOPCon is slightly higher. The highest PCEs of p-type TOPCon and n-type TOPCon solar cells are 26.0% and 25.8%, respectively. Despite the highest efficiency in small-area cells, limited progress has been achieved in p-type TOPCon solar cells for large are due to their lower carrier lifetime and inferior surface passivation with the boron-doped c-Si wafer. Nevertheless, it is of great importance to promoting the p-type TOPCon technology due to its lower price and well-established manufacturing procedures with slight modifications in the PERC solar cells production lines. The progress in different approaches to increase the efficiencies of p-type TOPCon solar cells has been reported in this review article and is expected to set valuable strategies to promote the passivation technology of p-type TOPCon, which could further increase the efficiency of TOPCon solar cells.

• 대한전자공학회논문지
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• 제27권3호
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• pp.108-115
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• 1990

고속 퓨리어변화(Fast Fourier Transform)연산용 2차원 시스토릭 어레이의 기본 구성요소인 단위 처리요소(Unit processing element)를 직접회로로 설계, 제작하고 제작된 칩을 평가하였다. 설계된 칩은 FFT 연산을 위한 데이타셔플링 기능과 반쪽 버터플라이 연산기능을 수행한다. 약 6,500여개의 트랜지스터로 구성된 이 칩은 표준셀 방식으로 설계되었으며, 2미크론 이중 금속 P-Well CMOS 공정으로 제작되었다. 제작된 칩을 웨이퍼 상태로 프로브카드를 이용하여 평가하였으며 그 결과, 20MHz 클럭 주파수에서 반쪽 버터플라이 연산이 0.5${\mu}sec$에 수행됨을 확인하였다. 본 논문에서 설계, 제작된 칩을 이용하여 1024-point FFT를 연산하는 경우 11.2${\mu}sec$의 시간이 소요될 것으로 예상된다.

• ETRI Journal
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• 제25권6호
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• pp.503-509
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• 2003

Selective epitaxial growth (SEG) of silicon has attracted considerable attention for its good electrical properties and advantages in building microstructures in high-density devices. However, SEG problems, such as an unclear process window, selectivity loss, and nonuniformity have often made application difficult. In our study, we derived processing diagrams for SEG from thermodynamics on gas-phase reactions so that we could predict the SEG process zone for low pressure chemical vapor deposition. In addition, with the help of both the concept of the effective supersaturation ratio and three kinds of E-beam patterns, we evaluated and controlled selectivity loss and non-uniformity in SEG, which is affected by the loading effect. To optimize the SEG process, we propose two practical methods: One deals with cleaning the wafer, and the other involves inserting dummy active patterns into the wide insulator to prevent the silicon from nucleating.