• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.5-11
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• 2006

One of the most important is to insure that a new circuit design is qualified far release before it is scheduled for manufacturing, test, assembly and delivery. Due to various causes, there happens to be a low yield in the wafer process. Wafer test is a critical process in analyzing the chip characteristics in the EDS(electric die sorting) using analytic tools -wafer map, wafer summary and datalog. In this paper, we propose new analytic map algorithms for DDI chip test data. Using the proposed analytic map algorithms, we expect to improve the yield, quality and analysis time.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.3
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• pp.267-274
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• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.46 no.2
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• pp.1-12
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• 2023

To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.11a
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• pp.147-151
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• 2003

Yield enhancement in semiconductor fabrication is important. Even though DRAM yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form patterns, it is usually an indication for the identification of equipment problems or process variations. In this paper describes the techniques to automatically classify a failure pattern using a fail bit map.

• Journal of the Korea Society for Simulation
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• v.14 no.1
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• pp.1-8
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• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• The Korean Journal of Applied Statistics
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• v.35 no.3
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• pp.407-419
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• 2022

The semiconductor fabrication process is complex and time-consuming. There are sometimes errors in the process, which results in defective die on the wafer bin map (WBM). We can detect the faulty WBM by finding some patterns caused by dies. When one manually seeks the failure on WBM, it takes a long time due to the enormous number of WBMs. We suggest a two-step approach to discover the probable pattern on the WBMs in this paper. The first step is to separate the normal WBMs from the defective WBMs. We adapt a hierarchical clustering for de-noising, which nicely performs this work by wisely tuning the number of minimum points and the cutting height. Once declared as a faulty WBM, then it moves to the next step. In the second step, we classify the patterns among the defective WBMs. For this purpose, we extract features from the WBM. Then machine learning algorithm classifies the pattern. We use a real WBM data set (WM-811K) released by Taiwan semiconductor manufacturing company.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1891-1894
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• 1999

We can classify the scratches after CMP process into micro-scratch and macro-scratches according to the scratch size, scratch intensity and defect map, etc. The micro-scratches on wafer after CMP process are discussed in this paper. From many causes, major factor that influences the formation of micro-scratch is known as particle size distribution of slurry.(1) It is indefinite what size or type of particle can cause micro-scratch on wafer surface, but there is possibility caused by large particle over 1um. The best way for controlling these large particle to inflow is to use the slurry filter on POU(Point of user). But the slurry filter(especially, depth-type filter) has sometimes the problem which makes more sever micro-scratches on wafer surface after CMP. We studied that depth-type slurry filter has what kind of week-points and the number of scratch could be reduced by lowering slurry flow rate and by using high spray bar which sprays DIW on polishing pad with high pressure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.267-269
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• 2003

반도체 웨이퍼 및 각종 박막의 면/비저항(sheet/resistivity resistance)의 측정에 비교적 간단히 측정할 수 있고 측정정확도가 높은 4탐침(four-point probe)방법이 널리 사용되고 있다 또한 4탐침 측정방법은 높은 분해능의 contour map작성과 ion implantation의 doping accuracy 및 doping uniformity의 측정에도 사용된다. 최근 재료의 소형, 박막화 경향으로 볼 때 정확한 비저항 측정의 필요성이 요구되고 있으며 이에 따라 4탐침 측정기술인 single 및 dual configuration method로 실리콘 웨이퍼에 대한 비저항의 측정 정확도를 고찰한 결과 dual configuration 측정방법이 single configuration측정 방법에 비하여 정밀 정확도가 더 좋은 것으로 고찰되었다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.11a
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• pp.248-251
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• 2020

전 반도체 제조 및 검사 공정 과정을 자동화하는 스마트 팩토리의 실현에 있어 제품 검수를 위한 검사 장비는 필수적이다. 하지만 딥 러닝 모델 학습을 위한 데이터 처리 과정에서 엔지니어가 전체 웨이퍼 영상에 대하여 결함 항목 라벨을 매칭하는 것은 현실적으로 불가능하기 때문에 소량의 라벨 (labeled) 데이터와 나머지 라벨이 없는 (unlabeled) 데이터를 적절히 활용해야 한다. 또한, 웨이퍼 영상에서 결함이 발생하는 빈도가 결함 종류별로 크게 차이가 나기 때문에 빈도가 적은 (minor) 결함은 잡음처럼 취급되어 올바른 분류가 되지 않는다. 본 논문에서는 소량의 라벨 데이터와 대량의 라벨이 없는 데이터를 동시에 활용하면서 결함 사이의 발생 빈도 불균등 문제를 해결하는 점진적 데이터 평준화 (progressive pseudo-labeling balancer)를 제안한다. 점진적 데이터 평준화를 이용해 분류 네트워크를 학습시키는 경우, 기존의 테스트 정확도인 71.19%에서 6.07%-p 상승한 77.26%로 약 40%의 라벨 데이터가 추가된 것과 같은 성능을 보였다.

• Journal of the Korea Society of Computer and Information
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• v.27 no.5
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• pp.55-67
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• 2022

Sensor data can provide fault diagnosis for equipment. However, the cause analysis for fault results of equipment is not often provided. In this study, we propose an explainable convolutional neural network framework for the sensor-based time series classification model. We used sensor-based time series dataset, acquired from vehicles equipped with sensors, and the Wafer dataset, acquired from manufacturing process. Moreover, we used Cycle Signal dataset, acquired from real world mechanical equipment, and for Data augmentation methods, scaling and jittering were used to train our deep learning models. In addition, our proposed classification models are convolutional neural network based models, FCN, 1D-CNN, and ResNet, to compare evaluations for each model. Our experimental results show that the ResNet provides promising results in the context of time series classification with accuracy and F1 Score reaching 95%, improved by 3% compared to the previous study. Furthermore, we propose XAI methods, Class Activation Map and Layer Visualization, to interpret the experiment result. XAI methods can visualize the time series interval that shows important factors for sensor data classification.