• 반도체디스플레이기술학회지
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• 제21권2호
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• pp.57-67
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• 2022

The curing characteristics of naphthalene type epoxy resin systems according to the change of curing agent were investigated to develop a new next-generation EMC(Epoxy Molding Compound) with excellent warpage characteristics, low thermal expansion, and excellent fluidity for WLP(Wafer Level Package). As epoxy resins, DGEBA, which are representative bisphenol type epoxy resins, NE-16, which are the base resins of naphthalene type epoxy resins, and NET-OH, NET-MA, and NET-Epoxy resins newly synthesized based on NE-16 were used. As a curing agent, DDM (Diamino Diphenyl Methane) and CBN resin with naphthalene moiety were used. The curing reaction characteristics of these epoxy resin systems with curing agents were analyzed through thermal analysis experiments. In terms of curing reaction mechanism, DGEBA and NET-OH resin systems follow the nth curing reaction mechanism, and NE-16, NET-MA and NET-Epoxy resin systems follow the autocatalytic curing reaction mechanism in the case of epoxy resin systems using DDM as curing agent. On the other hand, it was found that all of them showed the nth curing reaction mechanism in the case of epoxy resin systems using CBN as the curing agent. Comparing the curing reaction rate, the epoxy resin systems using CBN as the curing agent showed a faster curing reaction rate than them with DDM as a hardener in the case of DGEBA and NET-OH epoxy resin systems following the same nth curing reaction mechanism, and the epoxy resin systems with a different curing mechanism using CBN as a curing agent showed a faster curing reaction rate than DDM hardener systems except for the NE-16 epoxy resin system. These reasons were comparatively explained using the reaction rate parameters obtained through thermal analysis experiments. Based on these results, low thermal expansion, warpage reduction, and curing reaction rate in the epoxy resin systems can be improved by using CBN curing agent with a naphthalene moiety.

• 마이크로전자및패키징학회지
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• 제12권3호
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• pp.197-205
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• 2005

RF MEMS 기술에서 패키지의 개발은 매우 중요하다. RF MEMS 패키지는 소형화, hermetic 특성, 높은 RF 성능 및 신뢰성을 갖도록 설계되어야 한다. 또한 가능한 저온의 패키징 공정이 가능해야 한다. 본 연구에서는 저온 공정을 이용한 RF MEMS 소자의 hermetic 웨이퍼 레벨 패키징을 제안하였다. Hermetic sealing을 위하여 약 $300{\times}C$의 Au-Sn 공정 접합 (eutectic bonding) 기술을 사용하였으며, Au-Sn의 조합으로 형성된 sealing부의 폭은 $70{\mu}m$이었다. 소자의 전기적 연결을 위하여 기판에 수직 via hole을 형성하고 전기도금 (electroplating) 방법을 이용하여 Cu로 채웠다. 완성된 RF MEMS 패키지의 최종 크기는 $1mm\times1mm\times700{\mu}m$이었다. 패키징 공정의 최적화 및 $O_2$ 플라즈마 애싱 공정을 통하여 접합 계면 및 via hole의 void들을 제거할 수 있었다. 또한 패키지의 전단 강도 및 hermeticity는 MIL-STD-883F의 규격을 만족하였으며 패키지 내부에서 오염 및 기타 유기 물질은 발생하지 않았다. 패키지의 삽입 손실은 2 GHz에서 0.075 dB로 매우 작았으며, 여러 종류의 신뢰성 시험 결과 패키지의 파손 및 성능의 감소는 발견되지 않았다.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 3rd Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.121-145
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• 2001

Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• 마이크로전자및패키징학회지
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• 제16권1호
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• pp.27-31
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• 2009

본 논문에서는 웨이퍼 레벨 기술을 이용한 CIS용 폴리머 접합 기술을 연구하고 접합 후의 warpage 분석과 개별 패키지의 신뢰성 테스트를 수행하였다. 균일한 접합 높이를 유지하기 위하여 glass 웨이퍼 상에 dam을 형성하고 접합용 폴리머 층을 patterning하여 Si과 glass 웨이퍼의 접합 테스트를 수행하였다. Si 웨이퍼의 접합온도, 접합 압력 그리고 접합 층이 낮을수록 warpage 결과가 감소하였으며 접합시간과 승온 시간이 짧을수록 warpage 결과가 증가하는 것을 확인하였다. 접합 된 웨이퍼를 dicing 하여 각 개별 칩 단위로 TC, HTC, Humidity soak의 신뢰성 테스트를 수행하였으며 warpage 결과가 패키지의 신뢰성 결과에 미치는 영향은 미비한 것으로 확인되었다.

• 한국표면공학회지
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• 제36권2호
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• pp.214-225
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• 2003

Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.

• 마이크로전자및패키징학회지
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• 제19권2호
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.478-480
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• 2004

다이아몬드 톱날을 이용한 얇은 Si 웨이퍼의 기계적인 다이싱은 chipping, crack 등의 문제점을 발생시킨다. 또한 stacked die 나 multi-chip등과 같은 3D-WLP(wafer level package)에서 via를 생성하기 위해 현재 사용되는 화학적 etching은 공정속도가 느리고 제어가 힘들며, 공정이 복잡하다는 문제점을 가지고 있다. 이러한 문제점을 해결하기 위해 현재 연구되고 있는 분야가 레이저를 이용한 웨이퍼 다이싱 및 드릴링이다. 본 논문에서는 UV 레이저를 이용한 얇은 Si 웨이퍼 다이싱 및 드릴링 시스템에 대해 소개하고, 웨이퍼 다이싱 및 드릴링 실험결과를 바탕으로 적절한 레이저 및 공정 매개변수에 대해 설명한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.