• Journal of the Korean Solar Energy Society
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• v.33 no.2
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• pp.11-17
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• 2013

Silicon nitride($SiN_x:H$) deposited by radio frequency plasma enhanced chemical vapor deposition(RF-PECVD) is commonly used for anti-reflection coating and passivation in crystalline silicon solar cell fabrication. In this paper, characteristics of the deposited silicon nitride was studied with change of working pressure, deposition temperature, gas ratio of $NH_3$ and $SiH_4$, and RF power during deposition. The deposition rate, refractive index and effective lifetime were analyzed. The (100) p-type silicon wafers with one-side polished, $660-690{\mu}m$, and resistivity $1-10{\Omega}{\cdot}cm$ were used. As a result, when the working pressure increased, the deposition rate of SiNx was increased while the effective life time for the $SiN_x$-deposited wafer was decreased. The result regarding deposition temperature, gas ratio and RF power changes would be explained in detail below. In this paper, the optimized condition in silicon nitride deposition for silicon solar cell was obtained as 1.0 Torr for the working pressure, $400^{\circ}C$ for deposition temperature, 500 W for RF power and 0.88 for $NH_3/SiH_4$ gas ratio. The silicon nitride layer deposited in this condition showed the effective life time of > $1400{\mu}s$ and the surface recombination rate of 25 cm/s. The crystalline silicon solar cell fabricated with this SiNx coating showed 18.1% conversion efficiency.

• Journal of the Optical Society of Korea
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• v.19 no.6
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• pp.687-694
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• 2015

A photoluminescence (PL) imaging method using a vision camera was employed to inspect InGaN/GaN quantum-well light-emitting diode (LED) epi-wafers. The PL image revealed dark spot defective regions (DSDRs) as well as a spatial map of integrated PL intensity of the epi-wafer. The Shockley-Read-Hall (SRH) nonradiative recombination coefficient increased with the size of the DSDRs. The high nonradiative recombination rates of the DSDRs resulted in degradation of the optical properties of the LED chips fabricated at the defective regions. Abnormal current-voltage characteristics with large forward leakages were also observed for LED chips with DSDRs, which could be due to parallel resistances bypassing the junction and/or tunneling through defects in the active region. It was found that the SRH nonradiative recombination process was dominant in the voltage range where the forward leakage by tunneling was observed. The results indicated that the DSDRs observed by PL imaging of LED epi-wafers were high density SRH nonradiative recombination centers which could affect the optical and electrical properties of the LED chips, and PL imaging can be an inspection method for evaluation of the epi-wafers and estimation of properties of the LED chips before fabrication.

• 한국태양에너지학회:학술대회논문집
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• 2011.11a
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• pp.51-55
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• 2011

In this paper, the optimized doping condition of crystalline silicon solar cells with 156 ${\times}$ 156 mm2 area was studied. To optimize the drive-in condition in the doping process, the other conditions except drive-in temperature and time were fixed. After etching 7 ${\mu}m$ of the surface to form the pyramidal structure, the silicon nitride deposited by the PECVD had 75~80 nm thickness and 2 to 2.1 for a refractive index. The silver and aluminium electrodes for front and back sheet, respectively, were formed by screen-printing method, followed by firing in $400-425-450-550-850^{\circ}C$ five-zone temperature conditions to make the ohmic contact. Drive-in temperature was changed in range of $828^{\circ}C$ to $860^{\circ}C$ and time was from 3 min to 40 min. The sheet resistance of wafer was fixed to avoid its effect on solar cell. The solar cell fabricated with various conditions showed the similar conversion efficiency of 17.4%. This experimental result showed the drive-in temperatures and times little influence on solar cell characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.1-8
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• 2000

We have achieved a high aspect ratio track-following microactuator (TFMA) which is capable of driving 0.3 ${\mu}m$ magnetic head for hard disk drive (HDD). it was fabricated on silicon on insulator (SOI) wafer with 20 ${\mu}m$ trick active silicon and 2 ${\mu}m$ thick thermally grown oxide and piggyback electrostatic principle was used for driving TFMA. The first vibration mode frequency of TFMA was 18.5 kHz which is enough for a recording density of higher than 10 Gb/in$^2$. Its displacement was 1.4 ${\mu}m$ when 15 V dc bias plus 15 V ac sinusoidal driving input was applied and its electrostatic force was 50 N. The fabricated actuator shows 7.51 dB of gain margin and 50.98$^{\circ}$ of phase margin for 2.21 kHz servo-bandwidth.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.51-59
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• 1993

A 4${\times}10^{19}cm^{3}$ carbon-doped base AlGaAs/GaAs HBY was grown using carbontetracholoride(CCl$_4$) by atmospheric pressure MOCVD. Abruptness of emitter-base junction was characterized by SIMS(secondary ion mass spectorscopy) and the doping concentration of base layer was confirmed by DXRD(double crystal X-ray diffractometry). Mesa-type HBTs were fabricated using wet etching and lift-off technique. The base sheet resistance of R$_{sheet}$=550${\Omega}$/square was measured using TLM(transmission line model) method. The fabricated transistor achieved a collector-base junction breakdown voltage of BV$_{CBO}$=25V and a critical collector current density of J$_{O}$=40kA/cm$^2$ at V$_{CE}$=2V. The 50$\times$100$\mu$$^2$ emitter transistor showed a common emitter DC current gain of h$_{FE}$=30 at a collector current density of JS1CT=5kA/cm$^2$ and a base current ideality factor of ηS1EBT=1.4. The high frequency characterization of 5$\times$50$\mu$m$^2$ emitter transistor was carried out by on-wafer S-parameter measurement at 0.1~18.1GHz. Current gain cutoff frequency of f$_{T}$=27GHz and maximum oscillation frequency of f$_{max}$=16GHz were obtained from the measured Sparameter and device parameters of small-signal lumped-element equivalent network were extracted using Libra software. The fabricated HBT was proved to be useful to high speed and power spplications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.661-669
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• 1999

A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.32-32
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• 2008

X-ray detector는 의료용, 산업용 등 다양한 분야에서 사용되어지고 있으며 기존의 Analog X-ray 방식의 환경오염, 저장공간 부족, 실시간 분석의 어려움 등의 문제점들을 해결하기 위하여 Digital X-ray로의 전환과 연구가 활발하며 이에 따른 관심도 높아지고 있는 살점이다. Digital X-ray detector는 p-영역과 n-영역 사이에 아무런 불순물을 도핑하지 않은 진성반도체(intrinsic semiconductor) 층을 접합시킨 이종접합 PIN 구조의 photodiode 이다. 이 소자는 역바이어스를 가해주면 p영역과 n영역 사이에서 캐리어 (carrier)가 존재하지 않는 공핍 영역이 발생하게 된다. 이런 공핍 영역에서 광흡수가 일어나면, 전자-정공 쌍이 발생한다. 그리고, 발생한 전자-정공 쌍에 전압이 역방향으로 인가되는 경우, 전자는 양의 전극으로 이동하고, 정공은 음의 전극으로 이동한다. 이와 같이, 발생한 캐리어들을 검출하여 전기적인 신호로 변환 시킨다. 고해상도의 Digital X-ray detector를 만들기 위해서는 누설전류에 의한 noise 감소와 소자의 높은 안정성과 내구성을 위한 높은 breakdown voltage를 가져야 한다. 본 연구에서는 Digital X-ray detector의 leakage current 감소와 breakdown voltage를 높이기 위하여 guradring과 gettering technology를 사용하여 전기적 특성을 분석하였다. 기판으로는 $10k\Omega{\cdot}cm$ resistivity를 갖으며, n-type <111>인 1mm 두께의 4인치 Si wafer를 사용하였다. 그리고 pixel pitch는 $100{\mu}m$이며 active area는 $80{\mu}m{\times}80{\mu}m$인 $32\times32$ array를 형성하여 X-ray를 조사하여 소자의 특성을 평가 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.5
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• pp.191-195
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• 2002

Chemical mechanical Polishing (CMP) process is widely used for the global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP process, deionized water (DIW) pressure, purified $N_2$ ($PN_2$) gas, point of use (POU) slurry filler and high spray bar (HSB) were installed. Our experimental results show that DW pressure and P$N_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.4
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• pp.161-168
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• 2001

Organic thin film transitors(TFTs) are of interest for use in broad area electronic applications. For example, in active matrix liquid crystal displays(AMLCDs), organic TFTs would allow the use of inexpensive, light-weight, flexible, and mechanically rugged plastic substrates as an alternative to the glass substrates needed for commonly used hydrogenated amorphous silicon(a-Si:H). Recently pentacene TFTs with carrier field effect, mobility as large as 2 $cm^2V^{-1}s^{-1}$ have been reported for TFTs fabricated on silicon substrates, and it is higher than that of a-Si:H. But these TFTs are fabricated on silicon wafer and $SiO_2$ was used as a gate insulator. $SiO_2$ deposition process requires a high insulator which is polyimide and photo acryl. We investigated trasfer and output characteristics of the thin film transistors having active layer of pentacene. We calculated field effect mobility and on/off ratio from transfer characteristics of pentacene thin film transistor, and measured IR absorption spectrum of polymide used as the gate dielectric layer. It was found that using the photo acryl as a gate insulator, threshold voltage decreased from -12.5 V to -7 V, field effect mobility increased from 0.012 $cm^2V^{-1}s^{-1}$ to 0.039 $cm^2V^{-1}s^{-1}$ , and on/off current ratio increased from $10^5\;to\;10^6$. It seems that TFTs using photo acryl gate insulator is apt to form channel than TFTs using polyimide gate insulator.